[RFC] Factor out common test classes; package them (#1412)

* Pull out common test utilities into a separate package

* Project a fat jar for test utilities

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>

8 files changed, 11 insertions, 8 deletions

diff --git a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
index feba5a24..2c746c99 100644
--- a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
@@ -5,8 +5,8 @@ package firrtlTests.transforms
 import firrtl.annotations.{CircuitName, ModuleName}
 import firrtl.transforms._
 import firrtl.{Transform, VerilogEmitter}
-import firrtlTests.LowTransformSpec
 import firrtl.FileUtils
+import firrtl.testutils.LowTransformSpec
 
 
 class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
diff --git a/src/test/scala/firrtlTests/transforms/CombineCatsSpec.scala b/src/test/scala/firrtlTests/transforms/CombineCatsSpec.scala
index 6ac2d14e..f2672bce 100644
--- a/src/test/scala/firrtlTests/transforms/CombineCatsSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/CombineCatsSpec.scala
@@ -6,8 +6,8 @@ import firrtl.PrimOps._
 import firrtl._
 import firrtl.ir.DoPrim
 import firrtl.transforms.{CombineCats, MaxCatLenAnnotation}
-import firrtlTests.FirrtlFlatSpec
-import firrtlTests.FirrtlCheckers._
+import firrtl.testutils.FirrtlFlatSpec
+import firrtl.testutils.FirrtlCheckers._
 
 class CombineCatsSpec extends FirrtlFlatSpec {
   private val transforms = Seq(new IRToWorkingIR, new CombineCats)
diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala
index 971e8a1d..c96517ad 100644
--- a/src/test/scala/firrtlTests/transforms/DedupTests.scala
+++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala
@@ -6,6 +6,7 @@ package transforms
 import firrtl.RenameMap
 import firrtl.annotations._
 import firrtl.transforms.{DedupModules, NoCircuitDedupAnnotation}
+import firrtl.testutils._
 
 
 /**
diff --git a/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala b/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
index b4ecf058..c280f134 100644
--- a/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
@@ -5,6 +5,7 @@ import firrtl.annotations.{CircuitName, ComponentName, ModuleName}
 import firrtl.transforms.{GroupAnnotation, GroupComponents, NoCircuitDedupAnnotation}
 import firrtl._
 import firrtl.ir._
+import firrtl.testutils._
 
 import FirrtlCheckers._
 
diff --git a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala
index 72b006ec..c5847364 100644
--- a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala
@@ -2,7 +2,7 @@
 
 package firrtlTests.transforms
 
-import firrtlTests.FirrtlFlatSpec
+import firrtl.testutils.FirrtlFlatSpec
 import firrtl._
 import firrtl.passes._
 import firrtl.passes.wiring.{WiringTransform, SourceAnnotation, SinkAnnotation}
diff --git a/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala b/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala
index 5c2412ae..d7c76167 100644
--- a/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala
+++ b/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala
@@ -3,8 +3,8 @@
 package firrtlTests.transforms
 
 import firrtl._
-import firrtlTests.FirrtlFlatSpec
-import firrtlTests.FirrtlCheckers._
+import firrtl.testutils._
+import firrtl.testutils.FirrtlCheckers.containLine
 
 class LegalizeClocksTransformSpec extends FirrtlFlatSpec {
   def compile(input: String): CircuitState =
diff --git a/src/test/scala/firrtlTests/transforms/RemoveResetSpec.scala b/src/test/scala/firrtlTests/transforms/RemoveResetSpec.scala
index b9d92a6a..9b020b8e 100644
--- a/src/test/scala/firrtlTests/transforms/RemoveResetSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/RemoveResetSpec.scala
@@ -4,8 +4,8 @@ package firrtlTests.transforms
 
 import org.scalatest.GivenWhenThen
 
-import firrtlTests.FirrtlFlatSpec
-import firrtlTests.FirrtlCheckers._
+import firrtl.testutils.FirrtlFlatSpec
+import firrtl.testutils.FirrtlCheckers._
 
 import firrtl.{CircuitState, WRef}
 import firrtl.ir.{Connect, Mux}
diff --git a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
index 089f4a10..e26b0445 100644
--- a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
+++ b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
@@ -15,6 +15,7 @@ import firrtl.annotations.{
    Target
 }
 import firrtl.transforms.TopWiring._
+import firrtl.testutils._
 
 
 trait TopWiringTestsCommon extends FirrtlRunners {