diff options
| author | Jim Lawson | 2020-02-11 19:46:46 -0800 |
|---|---|---|
| committer | GitHub | 2020-02-12 03:46:46 +0000 |
| commit | 081848854ce692964491cfc4fa8e8ed47c13bcef (patch) | |
| tree | 8242846b6bc3131b36652ffd7519eda5e425f578 /src/test/scala/firrtlTests/transforms | |
| parent | 34681182a8fb611693c5ae32a296f306e72fb367 (diff) | |
Removed unused imports in src/test/ (#1381)
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/test/scala/firrtlTests/transforms')
| -rw-r--r-- | src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala | 3 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/transforms/TopWiringTest.scala | 8 |
2 files changed, 1 insertions, 10 deletions
diff --git a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala index 88095830..72b006ec 100644 --- a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala +++ b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala @@ -3,12 +3,9 @@ package firrtlTests.transforms import firrtlTests.FirrtlFlatSpec -import org.scalatest._ -import org.scalatest.prop._ import firrtl._ import firrtl.passes._ import firrtl.passes.wiring.{WiringTransform, SourceAnnotation, SinkAnnotation} -import firrtl.ir.Circuit import firrtl.annotations._ import firrtl.annotations.TargetToken.{Field, Index} diff --git a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala index 1c01d6d2..089f4a10 100644 --- a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala +++ b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala @@ -3,21 +3,15 @@ package firrtlTests package transforms -import org.scalatest.FlatSpec -import org.scalatest.Matchers -import org.scalatest.junit.JUnitRunner import java.io._ import firrtl._ -import firrtl.ir.{Circuit, Type, GroundType, IntWidth} +import firrtl.ir.{Type, GroundType, IntWidth} import firrtl.Parser -import firrtl.passes.PassExceptions import firrtl.annotations.{ - Named, CircuitName, ModuleName, ComponentName, - Annotation, Target } import firrtl.transforms.TopWiring._ |
