diff options
45 files changed, 15 insertions, 142 deletions
diff --git a/src/test/scala/firrtl/JsonProtocolSpec.scala b/src/test/scala/firrtl/JsonProtocolSpec.scala index 955abdc0..57c460a8 100644 --- a/src/test/scala/firrtl/JsonProtocolSpec.scala +++ b/src/test/scala/firrtl/JsonProtocolSpec.scala @@ -4,7 +4,6 @@ package firrtlTests import org.scalatest.FlatSpec import org.json4s._ -import org.json4s.native.JsonMethods._ import firrtl.annotations.{NoTargetAnnotation, JsonProtocol, InvalidAnnotationJSONException, HasSerializationHints, Annotation} diff --git a/src/test/scala/firrtlTests/AttachSpec.scala b/src/test/scala/firrtlTests/AttachSpec.scala index 1acb0d8b..1a5341e0 100644 --- a/src/test/scala/firrtlTests/AttachSpec.scala +++ b/src/test/scala/firrtlTests/AttachSpec.scala @@ -2,14 +2,9 @@ package firrtlTests -import java.io._ -import org.scalatest._ -import org.scalatest.prop._ import firrtl._ -import firrtl.annotations._ import firrtl.ir.Circuit import firrtl.passes._ -import firrtl.Parser.IgnoreInfo class InoutVerilogSpec extends FirrtlFlatSpec { diff --git a/src/test/scala/firrtlTests/CInferMDirSpec.scala b/src/test/scala/firrtlTests/CInferMDirSpec.scala index db8739fd..e03d1ab9 100644 --- a/src/test/scala/firrtlTests/CInferMDirSpec.scala +++ b/src/test/scala/firrtlTests/CInferMDirSpec.scala @@ -6,7 +6,6 @@ import firrtl._ import firrtl.ir._ import firrtl.passes._ import firrtl.transforms._ -import annotations._ class CInferMDir extends LowTransformSpec { object CInferMDirCheckPass extends Pass { diff --git a/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala b/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala index dc7158bb..2ff40282 100644 --- a/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala +++ b/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala @@ -3,8 +3,6 @@ package firrtlTests import firrtl._ -import firrtl.ir._ -import firrtl.passes._ import firrtl.transforms._ import annotations._ import java.io.File diff --git a/src/test/scala/firrtlTests/CheckInitializationSpec.scala b/src/test/scala/firrtlTests/CheckInitializationSpec.scala index 3af63c6e..cc3ed49f 100644 --- a/src/test/scala/firrtlTests/CheckInitializationSpec.scala +++ b/src/test/scala/firrtlTests/CheckInitializationSpec.scala @@ -2,11 +2,7 @@ package firrtlTests -import java.io._ -import org.scalatest._ -import org.scalatest.prop._ -import firrtl.{Parser, CircuitState, UnknownForm, Transform} -import firrtl.Parser.IgnoreInfo +import firrtl.{CircuitState, UnknownForm, Transform} import firrtl.passes._ class CheckInitializationSpec extends FirrtlFlatSpec { diff --git a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala index a4473fe7..25ce8742 100644 --- a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala +++ b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala @@ -7,7 +7,6 @@ import firrtl.ir._ import firrtl.passes._ import firrtl.transforms._ import firrtl.Mappers._ -import annotations._ import FirrtlCheckers._ import firrtl.PrimOps.AsClock diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala index dc70847a..8e17ceb1 100644 --- a/src/test/scala/firrtlTests/CompilerTests.scala +++ b/src/test/scala/firrtlTests/CompilerTests.scala @@ -4,7 +4,6 @@ package firrtlTests import org.scalatest.FlatSpec import org.scalatest.Matchers -import org.scalatest.junit.JUnitRunner import firrtl.ir.Circuit import firrtl.{ diff --git a/src/test/scala/firrtlTests/CustomTransformSpec.scala b/src/test/scala/firrtlTests/CustomTransformSpec.scala index 42ba031a..04cbf276 100644 --- a/src/test/scala/firrtlTests/CustomTransformSpec.scala +++ b/src/test/scala/firrtlTests/CustomTransformSpec.scala @@ -6,7 +6,6 @@ import firrtl.ir.Circuit import firrtl._ import firrtl.passes.Pass import firrtl.ir._ -import firrtl.annotations.{Annotation, NoTargetAnnotation} import firrtl.stage.{FirrtlSourceAnnotation, FirrtlStage, RunFirrtlTransformAnnotation} class CustomTransformSpec extends FirrtlFlatSpec { diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala index 620cc5f3..a9dbdda2 100644 --- a/src/test/scala/firrtlTests/DCETests.scala +++ b/src/test/scala/firrtlTests/DCETests.scala @@ -2,13 +2,11 @@ package firrtlTests -import firrtl.ir.Circuit import firrtl._ import firrtl.passes._ import firrtl.transforms._ import firrtl.annotations._ import firrtl.passes.memlib.SimpleTransform -import FirrtlCheckers._ import java.io.File import java.nio.file.Paths diff --git a/src/test/scala/firrtlTests/DriverSpec.scala b/src/test/scala/firrtlTests/DriverSpec.scala index 4df711b3..d55b7462 100644 --- a/src/test/scala/firrtlTests/DriverSpec.scala +++ b/src/test/scala/firrtlTests/DriverSpec.scala @@ -2,18 +2,18 @@ package firrtlTests -import java.io.{File, FileInputStream, FileWriter} +import java.io.{File, FileWriter} import org.scalatest.{FreeSpec, Matchers} -import firrtl.passes.{InlineAnnotation, InlineInstances} -import firrtl.passes.memlib.{InferReadWrite, InferReadWriteAnnotation, ReplSeqMem, ReplSeqMemAnnotation} +import firrtl.passes.InlineAnnotation +import firrtl.passes.memlib.{InferReadWriteAnnotation, ReplSeqMemAnnotation} import firrtl.transforms.BlackBoxTargetDirAnno import firrtl._ import firrtl.FileUtils import firrtl.annotations._ import firrtl.util.BackendCompilationUtilities -import scala.util.{Failure, Success, Try} +import scala.util.Success class ExceptingTransform extends Transform { def inputForm = HighForm diff --git a/src/test/scala/firrtlTests/ExpandWhensSpec.scala b/src/test/scala/firrtlTests/ExpandWhensSpec.scala index af82cc38..f7e694f3 100644 --- a/src/test/scala/firrtlTests/ExpandWhensSpec.scala +++ b/src/test/scala/firrtlTests/ExpandWhensSpec.scala @@ -2,13 +2,8 @@ package firrtlTests -import java.io._ -import org.scalatest._ -import org.scalatest.prop._ import firrtl._ import firrtl.passes._ -import firrtl.ir._ -import firrtl.Parser.IgnoreInfo class ExpandWhensSpec extends FirrtlFlatSpec { private val transforms = Seq( diff --git a/src/test/scala/firrtlTests/ExtModuleTests.scala b/src/test/scala/firrtlTests/ExtModuleTests.scala index 89c13b5e..207dc29e 100644 --- a/src/test/scala/firrtlTests/ExtModuleTests.scala +++ b/src/test/scala/firrtlTests/ExtModuleTests.scala @@ -2,9 +2,6 @@ package firrtlTests -import org.scalatest.Matchers -import firrtl._ - class ExtModuleTests extends FirrtlFlatSpec { "extmodule" should "serialize and re-parse equivalently" in { val input = diff --git a/src/test/scala/firrtlTests/FeatureSpec.scala b/src/test/scala/firrtlTests/FeatureSpec.scala index ef6c82ab..bdc61b14 100644 --- a/src/test/scala/firrtlTests/FeatureSpec.scala +++ b/src/test/scala/firrtlTests/FeatureSpec.scala @@ -2,8 +2,6 @@ package firrtlTests -import org.scalatest._ - // Miscellaneous Feature Checks class NestedSubAccessExecutionTest extends ExecutionTest("NestedSubAccessTester", "/features") diff --git a/src/test/scala/firrtlTests/FlattenTests.scala b/src/test/scala/firrtlTests/FlattenTests.scala index a63f6e13..19de9433 100644 --- a/src/test/scala/firrtlTests/FlattenTests.scala +++ b/src/test/scala/firrtlTests/FlattenTests.scala @@ -2,17 +2,8 @@ package firrtlTests -import org.scalatest.FlatSpec -import org.scalatest.Matchers -import org.scalatest.junit.JUnitRunner -import firrtl.ir.Circuit -import firrtl.Parser -import firrtl.passes.PassExceptions -import firrtl.annotations.{Annotation, CircuitName, ComponentName, ModuleName, Named} +import firrtl.annotations.{Annotation, CircuitName, ComponentName, ModuleName} import firrtl.transforms.{FlattenAnnotation, Flatten, NoCircuitDedupAnnotation} -import logger.{LogLevel, Logger} -import logger.LogLevel.Debug - /** * Tests deep inline transformation diff --git a/src/test/scala/firrtlTests/InferReadWriteSpec.scala b/src/test/scala/firrtlTests/InferReadWriteSpec.scala index db50b491..f2885fdf 100644 --- a/src/test/scala/firrtlTests/InferReadWriteSpec.scala +++ b/src/test/scala/firrtlTests/InferReadWriteSpec.scala @@ -5,8 +5,6 @@ package firrtlTests import firrtl._ import firrtl.ir._ import firrtl.passes._ -import firrtl.Mappers._ -import annotations._ import FirrtlCheckers._ class InferReadWriteSpec extends SimpleTransformSpec { diff --git a/src/test/scala/firrtlTests/InlineInstancesTests.scala b/src/test/scala/firrtlTests/InlineInstancesTests.scala index a3313825..3e606667 100644 --- a/src/test/scala/firrtlTests/InlineInstancesTests.scala +++ b/src/test/scala/firrtlTests/InlineInstancesTests.scala @@ -2,18 +2,9 @@ package firrtlTests -import org.scalatest.FlatSpec -import org.scalatest.Matchers -import org.scalatest.junit.JUnitRunner -import firrtl.ir.Circuit -import firrtl.Parser -import firrtl.passes.PassExceptions import firrtl.annotations._ import firrtl.passes.{InlineAnnotation, InlineInstances} import firrtl.transforms.NoCircuitDedupAnnotation -import logger.{LogLevel, Logger} -import logger.LogLevel.Debug - /** * Tests inline instances transformation diff --git a/src/test/scala/firrtlTests/IntegrationSpec.scala b/src/test/scala/firrtlTests/IntegrationSpec.scala index 732cd501..96703fc0 100644 --- a/src/test/scala/firrtlTests/IntegrationSpec.scala +++ b/src/test/scala/firrtlTests/IntegrationSpec.scala @@ -3,8 +3,6 @@ package firrtlTests import firrtl._ -import org.scalatest._ -import org.scalatest.prop._ import java.io.File diff --git a/src/test/scala/firrtlTests/LegalizeSpec.scala b/src/test/scala/firrtlTests/LegalizeSpec.scala index 2f76abc6..acc88619 100644 --- a/src/test/scala/firrtlTests/LegalizeSpec.scala +++ b/src/test/scala/firrtlTests/LegalizeSpec.scala @@ -2,7 +2,5 @@ package firrtlTests -import firrtl._ - class LegalizeExecutionTest extends ExecutionTest("Legalize", "/passes/Legalize") diff --git a/src/test/scala/firrtlTests/LowerTypesSpec.scala b/src/test/scala/firrtlTests/LowerTypesSpec.scala index 69379c51..b0e5727b 100644 --- a/src/test/scala/firrtlTests/LowerTypesSpec.scala +++ b/src/test/scala/firrtlTests/LowerTypesSpec.scala @@ -2,11 +2,7 @@ package firrtlTests -import java.io._ -import org.scalatest._ -import org.scalatest.prop._ import firrtl.Parser -import firrtl.ir.Circuit import firrtl.passes._ import firrtl.transforms._ import firrtl._ diff --git a/src/test/scala/firrtlTests/PassTests.scala b/src/test/scala/firrtlTests/PassTests.scala index 8350753d..3d2bc249 100644 --- a/src/test/scala/firrtlTests/PassTests.scala +++ b/src/test/scala/firrtlTests/PassTests.scala @@ -2,12 +2,9 @@ package firrtlTests -import java.io.{StringWriter,Writer} -import org.scalatest.{FlatSpec, Matchers} -import org.scalatest.junit.JUnitRunner +import org.scalatest.FlatSpec import firrtl.ir.Circuit -import firrtl.Parser.UseInfo -import firrtl.passes.{Pass, PassExceptions, RemoveEmpty} +import firrtl.passes.{PassExceptions, RemoveEmpty} import firrtl.transforms.DedupModules import firrtl._ import firrtl.annotations._ diff --git a/src/test/scala/firrtlTests/RemoveWiresSpec.scala b/src/test/scala/firrtlTests/RemoveWiresSpec.scala index 06e5dccd..1e578973 100644 --- a/src/test/scala/firrtlTests/RemoveWiresSpec.scala +++ b/src/test/scala/firrtlTests/RemoveWiresSpec.scala @@ -5,7 +5,6 @@ package firrtlTests import firrtl._ import firrtl.ir._ import firrtl.Mappers._ -import FirrtlCheckers._ import collection.mutable diff --git a/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala b/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala index e9ef3bcd..ca20c90e 100644 --- a/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala +++ b/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala @@ -3,10 +3,7 @@ package firrtlTests import firrtl._ -import firrtl.ir.Circuit -import firrtl.Parser.IgnoreInfo import firrtl.passes._ -import firrtl.transforms._ class ReplaceAccessesSpec extends FirrtlFlatSpec { val transforms = Seq( diff --git a/src/test/scala/firrtlTests/ReplaceTruncatingArithmeticSpec.scala b/src/test/scala/firrtlTests/ReplaceTruncatingArithmeticSpec.scala index b9c04e99..01adca3a 100644 --- a/src/test/scala/firrtlTests/ReplaceTruncatingArithmeticSpec.scala +++ b/src/test/scala/firrtlTests/ReplaceTruncatingArithmeticSpec.scala @@ -3,7 +3,6 @@ package firrtlTests import firrtl._ -import firrtl.ir._ import FirrtlCheckers._ class ReplaceTruncatingArithmeticSpec extends FirrtlFlatSpec { diff --git a/src/test/scala/firrtlTests/SimplifyMemsSpec.scala b/src/test/scala/firrtlTests/SimplifyMemsSpec.scala index 69f1a70e..ec947ecf 100644 --- a/src/test/scala/firrtlTests/SimplifyMemsSpec.scala +++ b/src/test/scala/firrtlTests/SimplifyMemsSpec.scala @@ -2,12 +2,6 @@ package firrtlTests -import java.io._ -import org.scalatest._ -import org.scalatest.prop._ -import firrtl.Parser -import firrtl.ir.Circuit -import firrtl.passes._ import firrtl.transforms._ import firrtl._ diff --git a/src/test/scala/firrtlTests/StringSpec.scala b/src/test/scala/firrtlTests/StringSpec.scala index aaf2a584..826343cf 100644 --- a/src/test/scala/firrtlTests/StringSpec.scala +++ b/src/test/scala/firrtlTests/StringSpec.scala @@ -2,16 +2,12 @@ package firrtlTests -import firrtl._ import firrtl.ir.StringLit import java.io._ import scala.sys.process._ import annotation.tailrec -import org.scalatest._ -import org.scalatest.prop._ -import org.scalatest.Assertions._ import org.scalacheck._ import org.scalacheck.Arbitrary._ diff --git a/src/test/scala/firrtlTests/UniquifySpec.scala b/src/test/scala/firrtlTests/UniquifySpec.scala index e64e9105..38063e5c 100644 --- a/src/test/scala/firrtlTests/UniquifySpec.scala +++ b/src/test/scala/firrtlTests/UniquifySpec.scala @@ -2,11 +2,7 @@ package firrtlTests -import java.io._ -import org.scalatest._ -import org.scalatest.prop._ import firrtl.Parser -import firrtl.ir.Circuit import firrtl.passes._ import firrtl._ import firrtl.annotations._ diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala index d2e2f295..8788bac7 100644 --- a/src/test/scala/firrtlTests/UnitTests.scala +++ b/src/test/scala/firrtlTests/UnitTests.scala @@ -3,8 +3,6 @@ package firrtlTests import java.io._ -import org.scalatest._ -import org.scalatest.prop._ import firrtl._ import firrtl.ir._ import firrtl.passes._ diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala index f7f3a0bb..ad8b8bf9 100644 --- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala +++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala @@ -2,16 +2,10 @@ package firrtlTests -import java.io._ - -import org.scalatest._ -import org.scalatest.prop._ import firrtl._ import firrtl.annotations._ -import firrtl.ir.Circuit import firrtl.passes._ import firrtl.transforms.VerilogRename -import firrtl.Parser.IgnoreInfo import FirrtlCheckers._ import firrtl.transforms.CombineCats diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala index 4c0e7f70..64afe12b 100644 --- a/src/test/scala/firrtlTests/WidthSpec.scala +++ b/src/test/scala/firrtlTests/WidthSpec.scala @@ -2,13 +2,8 @@ package firrtlTests -import java.io._ -import org.scalatest._ -import org.scalatest.prop._ import firrtl._ -import firrtl.ir.Circuit import firrtl.passes._ -import firrtl.Parser.IgnoreInfo class WidthSpec extends FirrtlFlatSpec { private def executeTest(input: String, expected: Seq[String], passes: Seq[Transform]) = { diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala index b2793494..3ec412d2 100644 --- a/src/test/scala/firrtlTests/WiringTests.scala +++ b/src/test/scala/firrtlTests/WiringTests.scala @@ -2,15 +2,9 @@ package firrtlTests -import java.io._ -import org.scalatest._ -import org.scalatest.prop._ import firrtl._ -import firrtl.ir.Circuit import firrtl.passes._ -import firrtl.Parser.IgnoreInfo import annotations._ -import wiring.WiringUtils._ import wiring._ class WiringTests extends FirrtlFlatSpec { diff --git a/src/test/scala/firrtlTests/ZeroWidthTests.scala b/src/test/scala/firrtlTests/ZeroWidthTests.scala index 96d03d08..b7f16034 100644 --- a/src/test/scala/firrtlTests/ZeroWidthTests.scala +++ b/src/test/scala/firrtlTests/ZeroWidthTests.scala @@ -2,12 +2,7 @@ package firrtlTests -import org.scalatest.Matchers -import java.io.{StringWriter,Writer} -import firrtl.ir.Circuit import firrtl._ -import firrtl.Parser.IgnoreInfo -import firrtl.Parser import firrtl.passes._ class ZeroWidthTests extends FirrtlFlatSpec { diff --git a/src/test/scala/firrtlTests/execution/VerilogExecution.scala b/src/test/scala/firrtlTests/execution/VerilogExecution.scala index 060554c0..f80a5ee6 100644 --- a/src/test/scala/firrtlTests/execution/VerilogExecution.scala +++ b/src/test/scala/firrtlTests/execution/VerilogExecution.scala @@ -4,7 +4,6 @@ import java.io.File import firrtl._ import firrtl.ir._ -import firrtlTests._ import firrtl.stage.{FirrtlCircuitAnnotation, FirrtlStage} import firrtl.options.TargetDirAnnotation diff --git a/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala b/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala index a4319e8b..e1b03728 100644 --- a/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala +++ b/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala @@ -2,8 +2,7 @@ package firrtlTests.fixed -import firrtl.{CircuitState, ChirrtlForm, LowFirrtlCompiler, Parser} -import firrtl.Parser.IgnoreInfo +import firrtl.{CircuitState, ChirrtlForm, LowFirrtlCompiler} import firrtlTests.FirrtlFlatSpec class FixedPointMathSpec extends FirrtlFlatSpec { diff --git a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala index a34145ac..baf1cda7 100644 --- a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala +++ b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala @@ -3,11 +3,8 @@ package firrtlTests package fixed -import java.io._ import firrtl._ -import firrtl.ir.Circuit import firrtl.passes._ -import firrtl.Parser.IgnoreInfo class FixedTypeInferenceSpec extends FirrtlFlatSpec { private def executeTest(input: String, expected: Seq[String], passes: Seq[Transform]) = { diff --git a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala index f5b16e45..30c606d2 100644 --- a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala +++ b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala @@ -4,9 +4,7 @@ package firrtlTests package fixed import firrtl._ -import firrtl.ir.Circuit import firrtl.passes._ -import firrtl.Parser.IgnoreInfo class RemoveFixedTypeSpec extends FirrtlFlatSpec { private def executeTest(input: String, expected: Seq[String], passes: Seq[Transform]) = { diff --git a/src/test/scala/firrtlTests/interval/IntervalMathSpec.scala b/src/test/scala/firrtlTests/interval/IntervalMathSpec.scala index 20fdeee1..f72fc292 100644 --- a/src/test/scala/firrtlTests/interval/IntervalMathSpec.scala +++ b/src/test/scala/firrtlTests/interval/IntervalMathSpec.scala @@ -3,11 +3,9 @@ package firrtlTests.interval import firrtl.Implicits.constraint2bound -import firrtl.{ChirrtlForm, CircuitState, LowFirrtlCompiler, Parser} +import firrtl.{ChirrtlForm, CircuitState, LowFirrtlCompiler} import firrtl.ir._ -import scala.math.BigDecimal.RoundingMode._ -import firrtl.Parser.IgnoreInfo import firrtl.constraint._ import firrtlTests.FirrtlFlatSpec diff --git a/src/test/scala/firrtlTests/interval/IntervalSpec.scala b/src/test/scala/firrtlTests/interval/IntervalSpec.scala index 37d79c84..056b0419 100644 --- a/src/test/scala/firrtlTests/interval/IntervalSpec.scala +++ b/src/test/scala/firrtlTests/interval/IntervalSpec.scala @@ -1,12 +1,9 @@ package firrtlTests package interval -import java.io._ - import firrtl._ import firrtl.ir.Circuit import firrtl.passes._ -import firrtl.Parser.IgnoreInfo import firrtl.passes.CheckTypes.InvalidConnect import firrtl.passes.CheckWidths.DisjointSqueeze diff --git a/src/test/scala/firrtlTests/options/RegistrationSpec.scala b/src/test/scala/firrtlTests/options/RegistrationSpec.scala index 43d71b6d..00b705df 100644 --- a/src/test/scala/firrtlTests/options/RegistrationSpec.scala +++ b/src/test/scala/firrtlTests/options/RegistrationSpec.scala @@ -3,14 +3,12 @@ package firrtlTests.options import org.scalatest.{FlatSpec, Matchers} -import scopt.OptionParser import java.util.ServiceLoader import firrtl.options.{RegisteredTransform, RegisteredLibrary, ShellOption} import firrtl.passes.Pass import firrtl.ir.Circuit import firrtl.annotations.NoTargetAnnotation -import firrtl.AnnotationSeq case object HelloAnnotation extends NoTargetAnnotation diff --git a/src/test/scala/firrtlTests/options/phases/WriteOutputAnnotationsSpec.scala b/src/test/scala/firrtlTests/options/phases/WriteOutputAnnotationsSpec.scala index 07aad53f..c5fc958c 100644 --- a/src/test/scala/firrtlTests/options/phases/WriteOutputAnnotationsSpec.scala +++ b/src/test/scala/firrtlTests/options/phases/WriteOutputAnnotationsSpec.scala @@ -6,11 +6,10 @@ import org.scalatest.{FlatSpec, Matchers} import java.io.File -import firrtl.{AnnotationSeq, EmittedFirrtlCircuitAnnotation, EmittedFirrtlCircuit} +import firrtl.AnnotationSeq import firrtl.annotations.{DeletedAnnotation, NoTargetAnnotation} import firrtl.options.{InputAnnotationFileAnnotation, OutputAnnotationFileAnnotation, Phase, WriteDeletedAnnotation} import firrtl.options.phases.{GetIncludes, WriteOutputAnnotations} -import firrtl.stage.FirrtlFileAnnotation class WriteOutputAnnotationsSpec extends FlatSpec with Matchers with firrtlTests.Utils { diff --git a/src/test/scala/firrtlTests/stage/FirrtlOptionsViewSpec.scala b/src/test/scala/firrtlTests/stage/FirrtlOptionsViewSpec.scala index 91594c1b..389e96b4 100644 --- a/src/test/scala/firrtlTests/stage/FirrtlOptionsViewSpec.scala +++ b/src/test/scala/firrtlTests/stage/FirrtlOptionsViewSpec.scala @@ -4,7 +4,6 @@ package firrtlTests.stage import org.scalatest.{FlatSpec, Matchers} -import firrtl.options._ import firrtl.stage._ import firrtl.{ir, NoneCompiler, Parser} diff --git a/src/test/scala/firrtlTests/stage/phases/AddCircuitSpec.scala b/src/test/scala/firrtlTests/stage/phases/AddCircuitSpec.scala index 3620ed49..ea4d8d72 100644 --- a/src/test/scala/firrtlTests/stage/phases/AddCircuitSpec.scala +++ b/src/test/scala/firrtlTests/stage/phases/AddCircuitSpec.scala @@ -4,7 +4,7 @@ package firrtlTests.stage.phases import org.scalatest.{FlatSpec, Matchers} -import firrtl.{AnnotationSeq, Parser} +import firrtl.Parser import firrtl.annotations.NoTargetAnnotation import firrtl.options.{OptionsException, Phase, PhasePrerequisiteException} import firrtl.stage.{CircuitOption, FirrtlCircuitAnnotation, FirrtlSourceAnnotation, InfoModeAnnotation, diff --git a/src/test/scala/firrtlTests/stage/phases/ChecksSpec.scala b/src/test/scala/firrtlTests/stage/phases/ChecksSpec.scala index 47aa9b5b..7eb1312d 100644 --- a/src/test/scala/firrtlTests/stage/phases/ChecksSpec.scala +++ b/src/test/scala/firrtlTests/stage/phases/ChecksSpec.scala @@ -8,7 +8,7 @@ import firrtl.stage._ import firrtl.{AnnotationSeq, ChirrtlEmitter, EmitAllModulesAnnotation, NoneCompiler} import firrtl.options.{OptionsException, OutputAnnotationFileAnnotation, Phase} -import firrtl.stage.phases.{AddImplicitOutputFile, Checks} +import firrtl.stage.phases.Checks class ChecksSpec extends FlatSpec with Matchers { diff --git a/src/test/scala/firrtlTests/stage/phases/CompilerSpec.scala b/src/test/scala/firrtlTests/stage/phases/CompilerSpec.scala index 7a3ab6b7..a8176316 100644 --- a/src/test/scala/firrtlTests/stage/phases/CompilerSpec.scala +++ b/src/test/scala/firrtlTests/stage/phases/CompilerSpec.scala @@ -5,7 +5,7 @@ package firrtlTests.stage.phases import org.scalatest.{FlatSpec, Matchers} import firrtl.{Compiler => _, _} -import firrtl.options.{Phase, PhasePrerequisiteException} +import firrtl.options.Phase import firrtl.stage.{CompilerAnnotation, FirrtlCircuitAnnotation, RunFirrtlTransformAnnotation} import firrtl.stage.phases.Compiler diff --git a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala index 88095830..72b006ec 100644 --- a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala +++ b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala @@ -3,12 +3,9 @@ package firrtlTests.transforms import firrtlTests.FirrtlFlatSpec -import org.scalatest._ -import org.scalatest.prop._ import firrtl._ import firrtl.passes._ import firrtl.passes.wiring.{WiringTransform, SourceAnnotation, SinkAnnotation} -import firrtl.ir.Circuit import firrtl.annotations._ import firrtl.annotations.TargetToken.{Field, Index} diff --git a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala index 1c01d6d2..089f4a10 100644 --- a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala +++ b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala @@ -3,21 +3,15 @@ package firrtlTests package transforms -import org.scalatest.FlatSpec -import org.scalatest.Matchers -import org.scalatest.junit.JUnitRunner import java.io._ import firrtl._ -import firrtl.ir.{Circuit, Type, GroundType, IntWidth} +import firrtl.ir.{Type, GroundType, IntWidth} import firrtl.Parser -import firrtl.passes.PassExceptions import firrtl.annotations.{ - Named, CircuitName, ModuleName, ComponentName, - Annotation, Target } import firrtl.transforms.TopWiring._ |