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authorchick2020-08-14 19:47:53 -0700
committerJack Koenig2020-08-14 19:47:53 -0700
commit6fc742bfaf5ee508a34189400a1a7dbffe3f1cac (patch)
tree2ed103ee80b0fba613c88a66af854ae9952610ce /src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
parentb516293f703c4de86397862fee1897aded2ae140 (diff)
All of src/ formatted with scalafmt
Diffstat (limited to 'src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala')
-rw-r--r--src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala76
1 files changed, 38 insertions, 38 deletions
diff --git a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
index 2c746c99..a52df4a9 100644
--- a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
@@ -8,9 +8,8 @@ import firrtl.{Transform, VerilogEmitter}
import firrtl.FileUtils
import firrtl.testutils.LowTransformSpec
-
class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
- def transform: Transform = new BlackBoxSourceHelper
+ def transform: Transform = new BlackBoxSourceHelper
private val moduleName = ModuleName("Top", CircuitName("Top"))
private val input = """
@@ -31,21 +30,21 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
| y <= a1.bar
""".stripMargin
private val output = """
- |circuit Top :
- |
- | extmodule AdderExtModule :
- | input foo : UInt<16>
- | output bar : UInt<16>
- |
- | defname = BBFAdd
- |
- | module Top :
- | input x : UInt<16>
- | output y : UInt<16>
- |
- | inst a1 of AdderExtModule
- | y <= a1.bar
- | a1.foo <= x
+ |circuit Top :
+ |
+ | extmodule AdderExtModule :
+ | input foo : UInt<16>
+ | output bar : UInt<16>
+ |
+ | defname = BBFAdd
+ |
+ | module Top :
+ | input x : UInt<16>
+ | output y : UInt<16>
+ |
+ | inst a1 of AdderExtModule
+ | y <= a1.bar
+ | a1.foo <= x
""".stripMargin
"annotated external modules with absolute path" should "appear in output directory" in {
@@ -61,8 +60,8 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
val module = new java.io.File("test_run_dir/AdderExtModule.v")
val fileList = new java.io.File(s"test_run_dir/${BlackBoxSourceHelper.defaultFileListName}")
- module.exists should be (true)
- fileList.exists should be (true)
+ module.exists should be(true)
+ fileList.exists should be(true)
module.delete()
fileList.delete()
@@ -80,8 +79,8 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
val module = new java.io.File("test_run_dir/AdderExtModule.v")
val fileList = new java.io.File(s"test_run_dir/${BlackBoxSourceHelper.defaultFileListName}")
- module.exists should be (true)
- fileList.exists should be (true)
+ module.exists should be(true)
+ fileList.exists should be(true)
module.delete()
fileList.delete()
@@ -96,8 +95,8 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
execute(input, output, annos)
- new java.io.File("test_run_dir/AdderExtModule.v").exists should be (true)
- new java.io.File(s"test_run_dir/${BlackBoxSourceHelper.defaultFileListName}").exists should be (true)
+ new java.io.File("test_run_dir/AdderExtModule.v").exists should be(true)
+ new java.io.File(s"test_run_dir/${BlackBoxSourceHelper.defaultFileListName}").exists should be(true)
}
"verilog header files" should "be available but not mentioned in the file list" in {
@@ -114,40 +113,41 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
// We'll copy the following resources to the test_run_dir via BlackBoxResourceAnno's
val resourceNames = Seq("ParameterizedViaHeaderAdderExtModule.v", "VerilogHeaderFile.vh")
- val annos = Seq(
- BlackBoxTargetDirAnno("test_run_dir")) ++ resourceNames.map{ n => BlackBoxResourceAnno(moduleName, "/blackboxes/" + n)}
+ val annos = Seq(BlackBoxTargetDirAnno("test_run_dir")) ++ resourceNames.map { n =>
+ BlackBoxResourceAnno(moduleName, "/blackboxes/" + n)
+ }
execute(pInput, pOutput, annos)
// Our resource files should exist in the test_run_dir,
for (n <- resourceNames)
- new java.io.File("test_run_dir/" + n).exists should be (true)
+ new java.io.File("test_run_dir/" + n).exists should be(true)
// but our file list should not include the verilog header file.
val fileListFile = new java.io.File(s"test_run_dir/${BlackBoxSourceHelper.defaultFileListName}")
- fileListFile.exists should be (true)
+ fileListFile.exists should be(true)
val fileList = FileUtils.getText(fileListFile)
- fileList.contains("ParameterizedViaHeaderAdderExtModule.v") should be (true)
- fileList.contains("VerilogHeaderFile.vh") should be (false)
+ fileList.contains("ParameterizedViaHeaderAdderExtModule.v") should be(true)
+ fileList.contains("VerilogHeaderFile.vh") should be(false)
}
- behavior of "BlackBox resources that do not exist"
+ behavior.of("BlackBox resources that do not exist")
it should "provide a useful error message for BlackBoxResourceAnno" in {
- val annos = Seq( BlackBoxTargetDirAnno("test_run_dir"),
- BlackBoxResourceAnno(moduleName, "/blackboxes/IDontExist.v") )
+ val annos = Seq(BlackBoxTargetDirAnno("test_run_dir"), BlackBoxResourceAnno(moduleName, "/blackboxes/IDontExist.v"))
- (the [BlackBoxNotFoundException] thrownBy { execute(input, "", annos) })
- .getMessage should include ("Did you misspell it?")
+ (the[BlackBoxNotFoundException] thrownBy { execute(input, "", annos) }).getMessage should include(
+ "Did you misspell it?"
+ )
}
it should "provide a useful error message for BlackBoxPathAnno" in {
val absPath = new java.io.File("src/test/resources/blackboxes/IDontExist.v").getCanonicalPath
- val annos = Seq( BlackBoxTargetDirAnno("test_run_dir"),
- BlackBoxPathAnno(moduleName, absPath) )
+ val annos = Seq(BlackBoxTargetDirAnno("test_run_dir"), BlackBoxPathAnno(moduleName, absPath))
- (the [BlackBoxNotFoundException] thrownBy { execute(input, "", annos) })
- .getMessage should include ("Did you misspell it?")
+ (the[BlackBoxNotFoundException] thrownBy { execute(input, "", annos) }).getMessage should include(
+ "Did you misspell it?"
+ )
}
}