All of src/ formatted with scalafmt

10 files changed, 1244 insertions, 1209 deletions

diff --git a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
index 2c746c99..a52df4a9 100644
--- a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
@@ -8,9 +8,8 @@ import firrtl.{Transform, VerilogEmitter}
 import firrtl.FileUtils
 import firrtl.testutils.LowTransformSpec
 
-
 class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
-   def transform: Transform = new BlackBoxSourceHelper
+  def transform: Transform = new BlackBoxSourceHelper
 
   private val moduleName = ModuleName("Top", CircuitName("Top"))
   private val input = """
@@ -31,21 +30,21 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
                         |   y <= a1.bar
                       """.stripMargin
   private val output = """
-                        |circuit Top :
-                        |
-                        |  extmodule AdderExtModule :
-                        |    input foo : UInt<16>
-                        |    output bar : UInt<16>
-                        |
-                        |    defname = BBFAdd
-                        |
-                        |  module Top :
-                        |   input x : UInt<16>
-                        |   output y : UInt<16>
-                        |
-                        |   inst a1 of AdderExtModule
-                        |   y <= a1.bar
-                        |   a1.foo <= x
+                         |circuit Top :
+                         |
+                         |  extmodule AdderExtModule :
+                         |    input foo : UInt<16>
+                         |    output bar : UInt<16>
+                         |
+                         |    defname = BBFAdd
+                         |
+                         |  module Top :
+                         |   input x : UInt<16>
+                         |   output y : UInt<16>
+                         |
+                         |   inst a1 of AdderExtModule
+                         |   y <= a1.bar
+                         |   a1.foo <= x
                       """.stripMargin
 
   "annotated external modules with absolute path" should "appear in output directory" in {
@@ -61,8 +60,8 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
     val module = new java.io.File("test_run_dir/AdderExtModule.v")
     val fileList = new java.io.File(s"test_run_dir/${BlackBoxSourceHelper.defaultFileListName}")
 
-    module.exists should be (true)
-    fileList.exists should be (true)
+    module.exists should be(true)
+    fileList.exists should be(true)
 
     module.delete()
     fileList.delete()
@@ -80,8 +79,8 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
     val module = new java.io.File("test_run_dir/AdderExtModule.v")
     val fileList = new java.io.File(s"test_run_dir/${BlackBoxSourceHelper.defaultFileListName}")
 
-    module.exists should be (true)
-    fileList.exists should be (true)
+    module.exists should be(true)
+    fileList.exists should be(true)
 
     module.delete()
     fileList.delete()
@@ -96,8 +95,8 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
 
     execute(input, output, annos)
 
-    new java.io.File("test_run_dir/AdderExtModule.v").exists should be (true)
-    new java.io.File(s"test_run_dir/${BlackBoxSourceHelper.defaultFileListName}").exists should be (true)
+    new java.io.File("test_run_dir/AdderExtModule.v").exists should be(true)
+    new java.io.File(s"test_run_dir/${BlackBoxSourceHelper.defaultFileListName}").exists should be(true)
   }
 
   "verilog header files" should "be available but not mentioned in the file list" in {
@@ -114,40 +113,41 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
     // We'll copy the following resources to the test_run_dir via BlackBoxResourceAnno's
     val resourceNames = Seq("ParameterizedViaHeaderAdderExtModule.v", "VerilogHeaderFile.vh")
 
-    val annos = Seq(
-      BlackBoxTargetDirAnno("test_run_dir")) ++ resourceNames.map{ n => BlackBoxResourceAnno(moduleName, "/blackboxes/" + n)}
+    val annos = Seq(BlackBoxTargetDirAnno("test_run_dir")) ++ resourceNames.map { n =>
+      BlackBoxResourceAnno(moduleName, "/blackboxes/" + n)
+    }
 
     execute(pInput, pOutput, annos)
 
     // Our resource files should exist in the test_run_dir,
     for (n <- resourceNames)
-      new java.io.File("test_run_dir/" + n).exists should be (true)
+      new java.io.File("test_run_dir/" + n).exists should be(true)
 
     //  but our file list should not include the verilog header file.
     val fileListFile = new java.io.File(s"test_run_dir/${BlackBoxSourceHelper.defaultFileListName}")
-    fileListFile.exists should be (true)
+    fileListFile.exists should be(true)
     val fileList = FileUtils.getText(fileListFile)
-    fileList.contains("ParameterizedViaHeaderAdderExtModule.v") should be (true)
-    fileList.contains("VerilogHeaderFile.vh") should be (false)
+    fileList.contains("ParameterizedViaHeaderAdderExtModule.v") should be(true)
+    fileList.contains("VerilogHeaderFile.vh") should be(false)
   }
 
-  behavior of "BlackBox resources that do not exist"
+  behavior.of("BlackBox resources that do not exist")
 
   it should "provide a useful error message for BlackBoxResourceAnno" in {
-    val annos = Seq( BlackBoxTargetDirAnno("test_run_dir"),
-                     BlackBoxResourceAnno(moduleName, "/blackboxes/IDontExist.v") )
+    val annos = Seq(BlackBoxTargetDirAnno("test_run_dir"), BlackBoxResourceAnno(moduleName, "/blackboxes/IDontExist.v"))
 
-    (the [BlackBoxNotFoundException] thrownBy { execute(input, "", annos) })
-      .getMessage should include ("Did you misspell it?")
+    (the[BlackBoxNotFoundException] thrownBy { execute(input, "", annos) }).getMessage should include(
+      "Did you misspell it?"
+    )
   }
 
   it should "provide a useful error message for BlackBoxPathAnno" in {
     val absPath = new java.io.File("src/test/resources/blackboxes/IDontExist.v").getCanonicalPath
-    val annos = Seq( BlackBoxTargetDirAnno("test_run_dir"),
-                     BlackBoxPathAnno(moduleName, absPath) )
+    val annos = Seq(BlackBoxTargetDirAnno("test_run_dir"), BlackBoxPathAnno(moduleName, absPath))
 
-    (the [BlackBoxNotFoundException] thrownBy { execute(input, "", annos) })
-      .getMessage should include ("Did you misspell it?")
+    (the[BlackBoxNotFoundException] thrownBy { execute(input, "", annos) }).getMessage should include(
+      "Did you misspell it?"
+    )
   }
 
 }
diff --git a/src/test/scala/firrtlTests/transforms/CombineCatsSpec.scala b/src/test/scala/firrtlTests/transforms/CombineCatsSpec.scala
index f2672bce..a916eac5 100644
--- a/src/test/scala/firrtlTests/transforms/CombineCatsSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/CombineCatsSpec.scala
@@ -14,9 +14,11 @@ class CombineCatsSpec extends FirrtlFlatSpec {
   private val annotations = Seq(new MaxCatLenAnnotation(12))
 
   private def execute(input: String, transforms: Seq[Transform], annotations: AnnotationSeq): CircuitState = {
-    val c = transforms.foldLeft(CircuitState(parse(input), UnknownForm, annotations)) {
-      (c: CircuitState, t: Transform) => t.runTransform(c)
-    }.circuit
+    val c = transforms
+      .foldLeft(CircuitState(parse(input), UnknownForm, annotations)) { (c: CircuitState, t: Transform) =>
+        t.runTransform(c)
+      }
+      .circuit
     CircuitState(c, UnknownForm, Seq(), None)
   }
 
@@ -86,11 +88,24 @@ class CombineCatsSpec extends FirrtlFlatSpec {
 
     // temp5 should get cat(cat(cat(in3, in2), cat(in4, in3)), cat(cat(in3, in2), cat(in4, in3)))
     result should containTree {
-      case DoPrim(Cat, Seq(
-        DoPrim(Cat, Seq(
-          DoPrim(Cat, Seq(WRef("in2", _, _, _), WRef("in1", _, _, _)), _, _),
-          DoPrim(Cat, Seq(WRef("in3", _, _, _), WRef("in2", _, _, _)), _, _)), _, _),
-        DoPrim(Cat, Seq(WRef("in4", _, _, _), WRef("in3", _, _, _)), _, _)), _, _) => true
+      case DoPrim(
+            Cat,
+            Seq(
+              DoPrim(
+                Cat,
+                Seq(
+                  DoPrim(Cat, Seq(WRef("in2", _, _, _), WRef("in1", _, _, _)), _, _),
+                  DoPrim(Cat, Seq(WRef("in3", _, _, _), WRef("in2", _, _, _)), _, _)
+                ),
+                _,
+                _
+              ),
+              DoPrim(Cat, Seq(WRef("in4", _, _, _), WRef("in3", _, _, _)), _, _)
+            ),
+            _,
+            _
+          ) =>
+        true
     }
   }
 
@@ -117,17 +132,19 @@ class CombineCatsSpec extends FirrtlFlatSpec {
 
     // should not contain any cat chains greater than 3
     result shouldNot containTree {
-      case DoPrim(Cat, Seq(_, DoPrim(Cat, Seq(_, DoPrim(Cat, _, _, _)), _, _)), _, _) => true
+      case DoPrim(Cat, Seq(_, DoPrim(Cat, Seq(_, DoPrim(Cat, _, _, _)), _, _)), _, _)                            => true
       case DoPrim(Cat, Seq(_, DoPrim(Cat, Seq(_, DoPrim(Cat, Seq(_, DoPrim(Cat, _, _, _)), _, _)), _, _)), _, _) => true
     }
 
     // temp2 should get cat(in3, cat(in2, in1))
     result should containTree {
-      case DoPrim(Cat, Seq(
-        WRef("in3", _, _, _),
-        DoPrim(Cat, Seq(
-          WRef("in2", _, _, _),
-          WRef("in1", _, _, _)), _, _)), _, _) => true
+      case DoPrim(
+            Cat,
+            Seq(WRef("in3", _, _, _), DoPrim(Cat, Seq(WRef("in2", _, _, _), WRef("in1", _, _, _)), _, _)),
+            _,
+            _
+          ) =>
+        true
     }
   }
 
@@ -152,8 +169,8 @@ class CombineCatsSpec extends FirrtlFlatSpec {
 
     val result = execute(input, transforms, Seq.empty)
     result shouldNot containTree {
-      case DoPrim(Cat, Seq(_, DoPrim(Add, _, _, _)), _, _) => true
-      case DoPrim(Cat, Seq(_, DoPrim(Sub, _, _, _)), _, _) => true
+      case DoPrim(Cat, Seq(_, DoPrim(Add, _, _, _)), _, _)                            => true
+      case DoPrim(Cat, Seq(_, DoPrim(Sub, _, _, _)), _, _)                            => true
       case DoPrim(Cat, Seq(_, DoPrim(Cat, Seq(_, DoPrim(Cat, _, _, _)), _, _)), _, _) => true
     }
   }
diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala
index 8ab3026c..8c2835dd 100644
--- a/src/test/scala/firrtlTests/transforms/DedupTests.scala
+++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala
@@ -10,8 +10,8 @@ import firrtl.transforms.{DedupModules, NoCircuitDedupAnnotation}
 import firrtl.testutils._
 
 /**
- * Tests inline instances transformation
- */
+  * Tests inline instances transformation
+  */
 class DedupModuleTests extends HighTransformSpec {
   case class MultiTargetDummyAnnotation(targets: Seq[Target], tag: Int) extends Annotation {
     override def update(renames: RenameMap): Seq[Annotation] = {
@@ -24,234 +24,236 @@ class DedupModuleTests extends HighTransformSpec {
   }
   def transform = new DedupModules
   "The module A" should "be deduped" in {
-     val input =
-        """circuit Top :
-          |  module Top :
-          |    inst a1 of A
-          |    inst a2 of A_
-          |  module A :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
-          |  module A_ :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |  module A_ :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
           """.stripMargin
-     val check =
-        """circuit Top :
-          |  module Top :
-          |    inst a1 of A
-          |    inst a2 of A
-          |  module A :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A
+        |  module A :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
           """.stripMargin
-     execute(input, check, Seq.empty)
+    execute(input, check, Seq.empty)
   }
   "The module A and B" should "be deduped" in {
-     val input =
-        """circuit Top :
-          |  module Top :
-          |    inst a1 of A
-          |    inst a2 of A_
-          |  module A :
-          |    output x: UInt<1>
-          |    inst b of B
-          |    x <= b.x
-          |  module A_ :
-          |    output x: UInt<1>
-          |    inst b of B_
-          |    x <= b.x
-          |  module B :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
-          |  module B_ :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A :
+        |    output x: UInt<1>
+        |    inst b of B
+        |    x <= b.x
+        |  module A_ :
+        |    output x: UInt<1>
+        |    inst b of B_
+        |    x <= b.x
+        |  module B :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |  module B_ :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
           """.stripMargin
-     val check =
-        """circuit Top :
-          |  module Top :
-          |    inst a1 of A
-          |    inst a2 of A
-          |  module A :
-          |    output x: UInt<1>
-          |    inst b of B
-          |    x <= b.x
-          |  module B :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A
+        |  module A :
+        |    output x: UInt<1>
+        |    inst b of B
+        |    x <= b.x
+        |  module B :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
           """.stripMargin
-     execute(input, check, Seq.empty)
+    execute(input, check, Seq.empty)
   }
   "The module A and B with comments" should "be deduped" in {
-     val input =
-        """circuit Top :
-          |  module Top :
-          |    inst a1 of A
-          |    inst a2 of A_
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    inst b of B @[yy 2:2]
-          |    x <= b.x @[yy 2:2]
-          |  module A_ : @[xx 1:1]
-          |    output x: UInt<1> @[xx 1:1]
-          |    inst b of B_ @[xx 1:1]
-          |    x <= b.x @[xx 1:1]
-          |  module B :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
-          |  module B_ :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A : @[yy 2:2]
+        |    output x: UInt<1> @[yy 2:2]
+        |    inst b of B @[yy 2:2]
+        |    x <= b.x @[yy 2:2]
+        |  module A_ : @[xx 1:1]
+        |    output x: UInt<1> @[xx 1:1]
+        |    inst b of B_ @[xx 1:1]
+        |    x <= b.x @[xx 1:1]
+        |  module B :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |  module B_ :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
           """.stripMargin
-     val check =
-        """circuit Top :
-          |  module Top :
-          |    inst a1 of A
-          |    inst a2 of A
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    inst b of B @[yy 2:2]
-          |    x <= b.x @[yy 2:2]
-          |  module B :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A
+        |  module A : @[yy 2:2]
+        |    output x: UInt<1> @[yy 2:2]
+        |    inst b of B @[yy 2:2]
+        |    x <= b.x @[yy 2:2]
+        |  module B :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
           """.stripMargin
-     execute(input, check, Seq.empty)
+    execute(input, check, Seq.empty)
   }
   "A_ but not A" should "be deduped if not annotated" in {
-     val input =
-        """circuit Top :
-          |  module Top :
-          |    inst a1 of A
-          |    inst a2 of A_
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    x <= UInt(1)
-          |  module A_ : @[xx 1:1]
-          |    output x: UInt<1> @[xx 1:1]
-          |    x <= UInt(1)
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A : @[yy 2:2]
+        |    output x: UInt<1> @[yy 2:2]
+        |    x <= UInt(1)
+        |  module A_ : @[xx 1:1]
+        |    output x: UInt<1> @[xx 1:1]
+        |    x <= UInt(1)
           """.stripMargin
-     val check =
-        """circuit Top :
-          |  module Top :
-          |    inst a1 of A
-          |    inst a2 of A_
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    x <= UInt(1)
-          |  module A_ : @[xx 1:1]
-          |    output x: UInt<1> @[xx 1:1]
-          |    x <= UInt(1)
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A : @[yy 2:2]
+        |    output x: UInt<1> @[yy 2:2]
+        |    x <= UInt(1)
+        |  module A_ : @[xx 1:1]
+        |    output x: UInt<1> @[xx 1:1]
+        |    x <= UInt(1)
           """.stripMargin
-     execute(input, check, Seq(dontDedup("A")))
+    execute(input, check, Seq(dontDedup("A")))
   }
   "The module A and A_" should "be deduped even with different port names and info, and annotations should remapped" in {
-     val input =
-        """circuit Top :
-          |  module Top :
-          |    output out: UInt<1>
-          |    inst a1 of A
-          |    inst a2 of A_
-          |    out <= and(a1.x, a2.y)
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    x <= UInt(1)
-          |  module A_ : @[xx 1:1]
-          |    output y: UInt<1> @[xx 1:1]
-          |    y <= UInt(1)
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    output out: UInt<1>
+        |    inst a1 of A
+        |    inst a2 of A_
+        |    out <= and(a1.x, a2.y)
+        |  module A : @[yy 2:2]
+        |    output x: UInt<1> @[yy 2:2]
+        |    x <= UInt(1)
+        |  module A_ : @[xx 1:1]
+        |    output y: UInt<1> @[xx 1:1]
+        |    y <= UInt(1)
         """.stripMargin
-     val check =
-        """circuit Top :
-          |  module Top :
-          |    output out: UInt<1>
-          |    inst a1 of A
-          |    inst a2 of A
-          |    out <= and(a1.x, a2.x)
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    x <= UInt(1)
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    output out: UInt<1>
+        |    inst a1 of A
+        |    inst a2 of A
+        |    out <= and(a1.x, a2.x)
+        |  module A : @[yy 2:2]
+        |    output x: UInt<1> @[yy 2:2]
+        |    x <= UInt(1)
         """.stripMargin
 
-     val mname = ModuleName("Top", CircuitName("Top"))
-     val finalState = execute(input, check, Seq(SingleTargetDummyAnnotation(ComponentName("a2.y", mname))))
-     finalState.annotations.collect({ case d: SingleTargetDummyAnnotation => d }).head should be(SingleTargetDummyAnnotation(ComponentName("a2.x", mname)))
+    val mname = ModuleName("Top", CircuitName("Top"))
+    val finalState = execute(input, check, Seq(SingleTargetDummyAnnotation(ComponentName("a2.y", mname))))
+    finalState.annotations.collect({ case d: SingleTargetDummyAnnotation => d }).head should be(
+      SingleTargetDummyAnnotation(ComponentName("a2.x", mname))
+    )
   }
 
   "Extmodules" should "with the same defname and parameters should dedup" in {
-     val input =
-        """circuit Top :
-          |  module Top :
-          |    output out: UInt<1>
-          |    inst a1 of A
-          |    inst a2 of A_
-          |    out <= and(a1.x, a2.y)
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    inst b of B
-          |    x <= b.u
-          |  module A_ : @[xx 1:1]
-          |    output y: UInt<1> @[xx 1:1]
-          |    inst c of C
-          |    y <= c.u
-          |  extmodule B : @[aa 3:3]
-          |    output u : UInt<1> @[aa 4:4]
-          |    defname = BB
-          |    parameter N = 0
-          |  extmodule C : @[bb 5:5]
-          |    output u : UInt<1> @[bb 6:6]
-          |    defname = BB
-          |    parameter N = 0
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    output out: UInt<1>
+        |    inst a1 of A
+        |    inst a2 of A_
+        |    out <= and(a1.x, a2.y)
+        |  module A : @[yy 2:2]
+        |    output x: UInt<1> @[yy 2:2]
+        |    inst b of B
+        |    x <= b.u
+        |  module A_ : @[xx 1:1]
+        |    output y: UInt<1> @[xx 1:1]
+        |    inst c of C
+        |    y <= c.u
+        |  extmodule B : @[aa 3:3]
+        |    output u : UInt<1> @[aa 4:4]
+        |    defname = BB
+        |    parameter N = 0
+        |  extmodule C : @[bb 5:5]
+        |    output u : UInt<1> @[bb 6:6]
+        |    defname = BB
+        |    parameter N = 0
         """.stripMargin
-     val check =
-        """circuit Top :
-          |  module Top :
-          |    output out: UInt<1>
-          |    inst a1 of A
-          |    inst a2 of A
-          |    out <= and(a1.x, a2.x)
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    inst b of B
-          |    x <= b.u
-          |  extmodule B : @[aa 3:3]
-          |    output u : UInt<1> @[aa 4:4]
-          |    defname = BB
-          |    parameter N = 0
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    output out: UInt<1>
+        |    inst a1 of A
+        |    inst a2 of A
+        |    out <= and(a1.x, a2.x)
+        |  module A : @[yy 2:2]
+        |    output x: UInt<1> @[yy 2:2]
+        |    inst b of B
+        |    x <= b.u
+        |  extmodule B : @[aa 3:3]
+        |    output u : UInt<1> @[aa 4:4]
+        |    defname = BB
+        |    parameter N = 0
         """.stripMargin
 
-     execute(input, check, Seq.empty)
+    execute(input, check, Seq.empty)
   }
 
   "Extmodules" should "with the different defname or parameters should NOT dedup" in {
-     def mkfir(defnames: (String, String), params: (String, String)) =
-       s"""circuit Top :
-          |  module Top :
-          |    output out: UInt<1>
-          |    inst a1 of A
-          |    inst a2 of A_
-          |    out <= and(a1.x, a2.y)
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    inst b of B
-          |    x <= b.u
-          |  module A_ : @[xx 1:1]
-          |    output y: UInt<1> @[xx 1:1]
-          |    inst c of C
-          |    y <= c.u
-          |  extmodule B : @[aa 3:3]
-          |    output u : UInt<1> @[aa 4:4]
-          |    defname = ${defnames._1}
-          |    parameter N = ${params._1}
-          |  extmodule C : @[bb 5:5]
-          |    output u : UInt<1> @[bb 6:6]
-          |    defname = ${defnames._2}
-          |    parameter N = ${params._2}
+    def mkfir(defnames: (String, String), params: (String, String)) =
+      s"""circuit Top :
+         |  module Top :
+         |    output out: UInt<1>
+         |    inst a1 of A
+         |    inst a2 of A_
+         |    out <= and(a1.x, a2.y)
+         |  module A : @[yy 2:2]
+         |    output x: UInt<1> @[yy 2:2]
+         |    inst b of B
+         |    x <= b.u
+         |  module A_ : @[xx 1:1]
+         |    output y: UInt<1> @[xx 1:1]
+         |    inst c of C
+         |    y <= c.u
+         |  extmodule B : @[aa 3:3]
+         |    output u : UInt<1> @[aa 4:4]
+         |    defname = ${defnames._1}
+         |    parameter N = ${params._1}
+         |  extmodule C : @[bb 5:5]
+         |    output u : UInt<1> @[bb 6:6]
+         |    defname = ${defnames._2}
+         |    parameter N = ${params._2}
         """.stripMargin
-     val diff_defname = mkfir(("BB", "CC"), ("0", "0"))
-     execute(diff_defname, diff_defname, Seq.empty)
-     val diff_params = mkfir(("BB", "BB"), ("0", "1"))
-     execute(diff_params, diff_params, Seq.empty)
+    val diff_defname = mkfir(("BB", "CC"), ("0", "0"))
+    execute(diff_defname, diff_defname, Seq.empty)
+    val diff_params = mkfir(("BB", "BB"), ("0", "1"))
+    execute(diff_params, diff_params, Seq.empty)
   }
 
   "Modules with aggregate ports that are bulk connected" should "NOT dedup if their port names differ" in {
@@ -426,12 +428,16 @@ class DedupModuleTests extends HighTransformSpec {
         |    wire b: UInt<1>
         |    x <= b
       """.stripMargin
-    val cs = execute(input, check, Seq(
-      dontTouch(ReferenceTarget("Top", "A", Nil, "b", Nil)),
-      dontTouch(ReferenceTarget("Top", "A_", Nil, "b", Nil))
-    ))
-    cs.annotations.toSeq should contain (dontTouch(ModuleTarget("Top", "Top").instOf("a1", "A").ref("b")))
-    cs.annotations.toSeq should contain (dontTouch(ModuleTarget("Top", "Top").instOf("a2", "A").ref("b")))
+    val cs = execute(
+      input,
+      check,
+      Seq(
+        dontTouch(ReferenceTarget("Top", "A", Nil, "b", Nil)),
+        dontTouch(ReferenceTarget("Top", "A_", Nil, "b", Nil))
+      )
+    )
+    cs.annotations.toSeq should contain(dontTouch(ModuleTarget("Top", "Top").instOf("a1", "A").ref("b")))
+    cs.annotations.toSeq should contain(dontTouch(ModuleTarget("Top", "Top").instOf("a2", "A").ref("b")))
     cs.annotations.toSeq should not contain dontTouch(ReferenceTarget("Top", "A_", Nil, "b", Nil))
   }
   "The module A and A_" should "be deduped with same annotation targets when there are a lot" in {
@@ -508,12 +514,24 @@ class DedupModuleTests extends HighTransformSpec {
     val annoAB = MultiTargetDummyAnnotation(Seq(A, B), 0)
     val annoA_B_ = MultiTargetDummyAnnotation(Seq(A_, B_), 1)
     val cs = execute(input, check, Seq(annoAB, annoA_B_))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      Top_a1, Top_a1_b
-    ), 0))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      Top_a2, Top_a2_b
-    ), 1))
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          Top_a1,
+          Top_a1_b
+        ),
+        0
+      )
+    )
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          Top_a2,
+          Top_a2_b
+        ),
+        1
+      )
+    )
   }
   "The module A and A_" should "be deduped with same annotations with same multi-targets, that share roots" in {
     val input =
@@ -555,15 +573,25 @@ class DedupModuleTests extends HighTransformSpec {
     val annoA = MultiTargetDummyAnnotation(Seq(A, A.instOf("b", "B")), 0)
     val annoA_ = MultiTargetDummyAnnotation(Seq(A_, A_.instOf("b", "B_")), 1)
     val cs = execute(input, check, Seq(annoA, annoA_))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      Top.module("Top").instOf("a1", "A"),
-      Top.module("Top").instOf("a1", "A").instOf("b", "B")
-    ),0))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      Top.module("Top").instOf("a2", "A"),
-      Top.module("Top").instOf("a2", "A").instOf("b", "B")
-    ),1))
-    cs.deletedAnnotations.isEmpty should be (true)
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          Top.module("Top").instOf("a1", "A"),
+          Top.module("Top").instOf("a1", "A").instOf("b", "B")
+        ),
+        0
+      )
+    )
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          Top.module("Top").instOf("a2", "A"),
+          Top.module("Top").instOf("a2", "A").instOf("b", "B")
+        ),
+        1
+      )
+    )
+    cs.deletedAnnotations.isEmpty should be(true)
   }
   "The deduping module A and A_" should "rename internal signals that have different names" in {
     val input =
@@ -600,12 +628,12 @@ class DedupModuleTests extends HighTransformSpec {
     val Top = CircuitTarget("Top")
     val A = Top.module("A")
     val A_ = Top.module("A_")
-    val annoA  = SingleTargetDummyAnnotation(A.ref("a"))
+    val annoA = SingleTargetDummyAnnotation(A.ref("a"))
     val annoA_ = SingleTargetDummyAnnotation(A_.ref("b"))
     val cs = execute(input, check, Seq(annoA, annoA_))
-    cs.annotations.toSeq should contain (annoA)
+    cs.annotations.toSeq should contain(annoA)
     cs.annotations.toSeq should not contain (SingleTargetDummyAnnotation(A.ref("b")))
-    cs.deletedAnnotations.isEmpty should be (true)
+    cs.deletedAnnotations.isEmpty should be(true)
   }
   "main" should "not be deduped even if it's the last module" in {
     val input =
@@ -691,14 +719,25 @@ class DedupModuleTests extends HighTransformSpec {
     val anno1 = MultiTargetDummyAnnotation(Seq(inst1, ref1), 0)
     val anno2 = MultiTargetDummyAnnotation(Seq(inst2, ref2), 1)
     val cs = execute(input, check, Seq(anno1, anno2))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      inst1, ref1
-    ),0))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      Top.module("Top").instOf("a_", "A").instOf("b", "B"),
-      Top.module("Top").instOf("a_", "A").instOf("b", "B").ref("foo")
-    ),1))
-    cs.deletedAnnotations.isEmpty should be (true)
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          inst1,
+          ref1
+        ),
+        0
+      )
+    )
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          Top.module("Top").instOf("a_", "A").instOf("b", "B"),
+          Top.module("Top").instOf("a_", "A").instOf("b", "B").ref("foo")
+        ),
+        1
+      )
+    )
+    cs.deletedAnnotations.isEmpty should be(true)
   }
 
   "The deduping module A and A_" should "rename nested instances that have different names" in {
@@ -746,14 +785,25 @@ class DedupModuleTests extends HighTransformSpec {
     val anno1 = MultiTargetDummyAnnotation(Seq(inst1, ref1), 0)
     val anno2 = MultiTargetDummyAnnotation(Seq(inst2, ref2), 1)
     val cs = execute(input, check, Seq(anno1, anno2))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      inst1, ref1
-    ),0))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      Top.module("Top").instOf("a_", "A").instOf("b", "B").instOf("c", "C").instOf("d", "D"),
-      Top.module("Top").instOf("a_", "A").instOf("b", "B").instOf("c", "C").instOf("d", "D").ref("foo")
-    ),1))
-    cs.deletedAnnotations.isEmpty should be (true)
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          inst1,
+          ref1
+        ),
+        0
+      )
+    )
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          Top.module("Top").instOf("a_", "A").instOf("b", "B").instOf("c", "C").instOf("d", "D"),
+          Top.module("Top").instOf("a_", "A").instOf("b", "B").instOf("c", "C").instOf("d", "D").ref("foo")
+        ),
+        1
+      )
+    )
+    cs.deletedAnnotations.isEmpty should be(true)
   }
 
   "Deduping modules with multiple instances" should "corectly rename instances" in {
@@ -801,50 +851,55 @@ class DedupModuleTests extends HighTransformSpec {
     val cInstances = bInstances.map(_.instOf("c", "C"))
     val annos = MultiTargetDummyAnnotation(bInstances ++ cInstances, 0)
     val cs = execute(input, check, Seq(annos))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      Top.instOf("b", "B"),
-      Top.instOf("b_", "B"),
-      Top.instOf("a1", "A").instOf("b_", "B"),
-      Top.instOf("a2", "A").instOf("b_", "B"),
-      Top.instOf("a1", "A").instOf("b", "B"),
-      Top.instOf("a2", "A").instOf("b", "B"),
-      Top.instOf("b", "B").instOf("c", "C"),
-      Top.instOf("b_", "B").instOf("c", "C"),
-      Top.instOf("a1", "A").instOf("b_", "B").instOf("c", "C"),
-      Top.instOf("a2", "A").instOf("b_", "B").instOf("c", "C"),
-      Top.instOf("a1", "A").instOf("b", "B").instOf("c", "C"),
-      Top.instOf("a2", "A").instOf("b", "B").instOf("c", "C")
-    ),0))
-    cs.deletedAnnotations.isEmpty should be (true)
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          Top.instOf("b", "B"),
+          Top.instOf("b_", "B"),
+          Top.instOf("a1", "A").instOf("b_", "B"),
+          Top.instOf("a2", "A").instOf("b_", "B"),
+          Top.instOf("a1", "A").instOf("b", "B"),
+          Top.instOf("a2", "A").instOf("b", "B"),
+          Top.instOf("b", "B").instOf("c", "C"),
+          Top.instOf("b_", "B").instOf("c", "C"),
+          Top.instOf("a1", "A").instOf("b_", "B").instOf("c", "C"),
+          Top.instOf("a2", "A").instOf("b_", "B").instOf("c", "C"),
+          Top.instOf("a1", "A").instOf("b", "B").instOf("c", "C"),
+          Top.instOf("a2", "A").instOf("b", "B").instOf("c", "C")
+        ),
+        0
+      )
+    )
+    cs.deletedAnnotations.isEmpty should be(true)
   }
 
   "dedup" should "properly rename target components after retyping" in {
     val input = """
-      |circuit top:
-      |  module top:
-      |    input ia: {z: {y: {x: UInt<1>}}, a: UInt<1>}
-      |    input ib: {a: {b: {c: UInt<1>}}, z: UInt<1>}
-      |    output oa: {z: {y: {x: UInt<1>}}, a: UInt<1>}
-      |    output ob: {a: {b: {c: UInt<1>}}, z: UInt<1>}
-      |    inst a of a
-      |    a.i.z.y.x <= ia.z.y.x
-      |    a.i.a <= ia.a
-      |    oa.z.y.x <= a.o.z.y.x
-      |    oa.a <= a.o.a
-      |    inst b of b
-      |    b.q.a.b.c <= ib.a.b.c
-      |    b.q.z <= ib.z
-      |    ob.a.b.c <= b.r.a.b.c
-      |    ob.z <= b.r.z
-      |  module a:
-      |    input i: {z: {y: {x: UInt<1>}}, a: UInt<1>}
-      |    output o: {z: {y: {x: UInt<1>}}, a: UInt<1>}
-      |    o <= i
-      |  module b:
-      |    input q: {a: {b: {c: UInt<1>}}, z: UInt<1>}
-      |    output r: {a: {b: {c: UInt<1>}}, z: UInt<1>}
-      |    r <= q
-      |""".stripMargin
+                  |circuit top:
+                  |  module top:
+                  |    input ia: {z: {y: {x: UInt<1>}}, a: UInt<1>}
+                  |    input ib: {a: {b: {c: UInt<1>}}, z: UInt<1>}
+                  |    output oa: {z: {y: {x: UInt<1>}}, a: UInt<1>}
+                  |    output ob: {a: {b: {c: UInt<1>}}, z: UInt<1>}
+                  |    inst a of a
+                  |    a.i.z.y.x <= ia.z.y.x
+                  |    a.i.a <= ia.a
+                  |    oa.z.y.x <= a.o.z.y.x
+                  |    oa.a <= a.o.a
+                  |    inst b of b
+                  |    b.q.a.b.c <= ib.a.b.c
+                  |    b.q.z <= ib.z
+                  |    ob.a.b.c <= b.r.a.b.c
+                  |    ob.z <= b.r.z
+                  |  module a:
+                  |    input i: {z: {y: {x: UInt<1>}}, a: UInt<1>}
+                  |    output o: {z: {y: {x: UInt<1>}}, a: UInt<1>}
+                  |    o <= i
+                  |  module b:
+                  |    input q: {a: {b: {c: UInt<1>}}, z: UInt<1>}
+                  |    output r: {a: {b: {c: UInt<1>}}, z: UInt<1>}
+                  |    r <= q
+                  |""".stripMargin
 
     case class DummyRTAnnotation(target: ReferenceTarget) extends SingleTargetAnnotation[ReferenceTarget] {
       def duplicate(n: ReferenceTarget) = DummyRTAnnotation(n)
@@ -853,7 +908,6 @@ class DedupModuleTests extends HighTransformSpec {
     val annA = DummyRTAnnotation(ReferenceTarget("top", "a", Nil, "i", Seq(TargetToken.Field("a"))))
     val annB = DummyRTAnnotation(ReferenceTarget("top", "b", Nil, "q", Seq(TargetToken.Field("a"))))
 
-
     val cs = CircuitState(Parser.parseString(input, Parser.IgnoreInfo), Seq(annA, annB))
 
     val deduper = new stage.transforms.Compiler(stage.Forms.Deduped, Nil)
@@ -871,7 +925,7 @@ class DedupModuleTests extends HighTransformSpec {
     val bPath = Seq((TargetToken.Instance("b"), TargetToken.OfModule("a")))
     val expectedAnnA = DummyRTAnnotation(ReferenceTarget("top", "top", aPath, "i", Seq(TargetToken.Field("a"))))
     val expectedAnnB = DummyRTAnnotation(ReferenceTarget("top", "top", aPath, "i", Seq(TargetToken.Field("a"))))
-    csDeduped.annotations.toSeq should contain (expectedAnnA)
-    csDeduped.annotations.toSeq should contain (expectedAnnB)
+    csDeduped.annotations.toSeq should contain(expectedAnnA)
+    csDeduped.annotations.toSeq should contain(expectedAnnB)
   }
 }
diff --git a/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala b/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
index fdb129a1..65544764 100644
--- a/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
@@ -17,75 +17,75 @@ class GroupComponentsSpec extends MiddleTransformSpec {
   def topComp(name: String): ComponentName = ComponentName(name, ModuleName(top, CircuitName(top)))
   "The register r" should "be grouped" in {
     val input =
-    s"""circuit $top :
-        |  module $top :
-        |    input clk: Clock
-        |    input data: UInt<16>
-        |    output out: UInt<16>
-        |    reg r: UInt<16>, clk
-        |    r <= data
-        |    out <= r
+      s"""circuit $top :
+         |  module $top :
+         |    input clk: Clock
+         |    input data: UInt<16>
+         |    output out: UInt<16>
+         |    reg r: UInt<16>, clk
+         |    r <= data
+         |    out <= r
       """.stripMargin
     val groups = Seq(
       GroupAnnotation(Seq(topComp("r")), "MyReg", "rInst", Some("_OUT"), Some("_IN"))
     )
     val check =
-     s"""circuit Top :
-        |  module $top :
-        |    input clk: Clock
-        |    input data: UInt<16>
-        |    output out: UInt<16>
-        |    inst rInst of MyReg
-        |    rInst.clk_IN <= clk
-        |    out <= rInst.r_OUT
-        |    rInst.data_IN <= data
-        |  module MyReg :
-        |    input clk_IN: Clock
-        |    output r_OUT: UInt<16>
-        |    input data_IN: UInt<16>
-        |    reg r: UInt<16>, clk_IN
-        |    r_OUT <= r
-        |    r <= data_IN
+      s"""circuit Top :
+         |  module $top :
+         |    input clk: Clock
+         |    input data: UInt<16>
+         |    output out: UInt<16>
+         |    inst rInst of MyReg
+         |    rInst.clk_IN <= clk
+         |    out <= rInst.r_OUT
+         |    rInst.data_IN <= data
+         |  module MyReg :
+         |    input clk_IN: Clock
+         |    output r_OUT: UInt<16>
+         |    input data_IN: UInt<16>
+         |    reg r: UInt<16>, clk_IN
+         |    r_OUT <= r
+         |    r <= data_IN
       """.stripMargin
     execute(input, check, groups)
   }
   "Grouping" should "work even when there are unused nodes" in {
     val input =
-    s"""circuit $top :
-        |  module $top :
-        |    input in: UInt<16>
-        |    output out: UInt<16>
-        |    node n = UInt<16>("h0")
-        |    wire w : UInt<16>
-        |    wire a : UInt<16>
-        |    wire b : UInt<16>
-        |    a <= UInt<16>("h0")
-        |    b <= a
-        |    w <= in
-        |    out <= w
+      s"""circuit $top :
+         |  module $top :
+         |    input in: UInt<16>
+         |    output out: UInt<16>
+         |    node n = UInt<16>("h0")
+         |    wire w : UInt<16>
+         |    wire a : UInt<16>
+         |    wire b : UInt<16>
+         |    a <= UInt<16>("h0")
+         |    b <= a
+         |    w <= in
+         |    out <= w
       """.stripMargin
     val groups = Seq(
       GroupAnnotation(Seq(topComp("w")), "Child", "inst", Some("_OUT"), Some("_IN"))
     )
     val check =
-     s"""circuit Top :
-        |  module $top :
-        |    input in: UInt<16>
-        |    output out: UInt<16>
-        |    inst inst of Child
-        |    node n = UInt<16>("h0")
-        |    wire a : UInt<16>
-        |    wire b : UInt<16>
-        |    out <= inst.w_OUT
-        |    inst.in_IN <= in
-        |    a <= UInt<16>("h0")
-        |    b <= a
-        |  module Child :
-        |    output w_OUT : UInt<16>
-        |    input in_IN : UInt<16>
-        |    wire w : UInt<16>
-        |    w_OUT <= w
-        |    w <= in_IN
+      s"""circuit Top :
+         |  module $top :
+         |    input in: UInt<16>
+         |    output out: UInt<16>
+         |    inst inst of Child
+         |    node n = UInt<16>("h0")
+         |    wire a : UInt<16>
+         |    wire b : UInt<16>
+         |    out <= inst.w_OUT
+         |    inst.in_IN <= in
+         |    a <= UInt<16>("h0")
+         |    b <= a
+         |  module Child :
+         |    output w_OUT : UInt<16>
+         |    input in_IN : UInt<16>
+         |    wire w : UInt<16>
+         |    w_OUT <= w
+         |    w <= in_IN
       """.stripMargin
     execute(input, check, groups)
   }
@@ -116,8 +116,8 @@ class GroupComponentsSpec extends MiddleTransformSpec {
          |    out <= UInt(2)
       """.stripMargin
     val annotations = Seq(
-      GroupAnnotation(Seq(topComp("c1a"), topComp("c2a")/*, topComp("asum")*/), "A", "cA", Some("_OUT"), Some("_IN")),
-      GroupAnnotation(Seq(topComp("c1b"), topComp("c2b")/*, topComp("bsum")*/), "B", "cB", Some("_OUT"), Some("_IN")),
+      GroupAnnotation(Seq(topComp("c1a"), topComp("c2a") /*, topComp("asum")*/ ), "A", "cA", Some("_OUT"), Some("_IN")),
+      GroupAnnotation(Seq(topComp("c1b"), topComp("c2b") /*, topComp("bsum")*/ ), "B", "cB", Some("_OUT"), Some("_IN")),
       NoCircuitDedupAnnotation
     )
     val check =
@@ -380,7 +380,7 @@ class GroupComponentsIntegrationSpec extends FirrtlFlatSpec {
   def topComp(name: String): ComponentName = ComponentName(name, ModuleName("Top", CircuitName("Top")))
   "Grouping" should "properly set kinds" in {
     val input =
-     """circuit Top :
+      """circuit Top :
         |  module Top :
         |    input clk: Clock
         |    input data: UInt<16>
@@ -397,13 +397,13 @@ class GroupComponentsIntegrationSpec extends FirrtlFlatSpec {
       Seq(new GroupComponents)
     )
     result should containTree {
-      case Connect(_, WSubField(WRef("inst",_, InstanceKind,_), "data_IN", _,_), WRef("data",_,_,_)) => true
+      case Connect(_, WSubField(WRef("inst", _, InstanceKind, _), "data_IN", _, _), WRef("data", _, _, _)) => true
     }
     result should containTree {
-      case Connect(_, WSubField(WRef("inst",_, InstanceKind,_), "clk_IN", _,_), WRef("clk",_,_,_)) => true
+      case Connect(_, WSubField(WRef("inst", _, InstanceKind, _), "clk_IN", _, _), WRef("clk", _, _, _)) => true
     }
     result should containTree {
-      case Connect(_, WRef("out",_,_,_), WSubField(WRef("inst",_, InstanceKind,_), "r_OUT", _,_)) => true
+      case Connect(_, WRef("out", _, _, _), WSubField(WRef("inst", _, InstanceKind, _), "r_OUT", _, _)) => true
     }
   }
 }
diff --git a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala
index c5847364..0043cb1f 100644
--- a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala
@@ -5,36 +5,25 @@ package firrtlTests.transforms
 import firrtl.testutils.FirrtlFlatSpec
 import firrtl._
 import firrtl.passes._
-import firrtl.passes.wiring.{WiringTransform, SourceAnnotation, SinkAnnotation}
+import firrtl.passes.wiring.{SinkAnnotation, SourceAnnotation, WiringTransform}
 import firrtl.annotations._
 import firrtl.annotations.TargetToken.{Field, Index}
 
-
 class InferWidthsWithAnnosSpec extends FirrtlFlatSpec {
-  private def executeTest(input: String,
-    check: String,
-    transforms: Seq[Transform],
-    annotations: Seq[Annotation]) = {
+  private def executeTest(input: String, check: String, transforms: Seq[Transform], annotations: Seq[Annotation]) = {
     val start = CircuitState(parse(input), ChirrtlForm, annotations)
-    val end = transforms.foldLeft(start) {
-      (c: CircuitState, t: Transform) => t.runTransform(c)
+    val end = transforms.foldLeft(start) { (c: CircuitState, t: Transform) =>
+      t.runTransform(c)
     }
-    val resLines = end.circuit.serialize.split("\n") map normalized
-    val checkLines = parse(check).serialize.split("\n") map normalized
+    val resLines = end.circuit.serialize.split("\n").map(normalized)
+    val checkLines = parse(check).serialize.split("\n").map(normalized)
 
-    resLines should be (checkLines)
+    resLines should be(checkLines)
   }
 
   "CheckWidths on wires with unknown widths" should "result in an error" in {
-    val transforms = Seq(
-      ToWorkingIR,
-      CheckHighForm,
-      ResolveKinds,
-      InferTypes,
-      CheckTypes,
-      ResolveFlows,
-      new InferWidths,
-      CheckWidths)
+    val transforms =
+      Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes, ResolveFlows, new InferWidths, CheckWidths)
 
     val input =
       """circuit Top :
@@ -55,19 +44,15 @@ class InferWidthsWithAnnosSpec extends FirrtlFlatSpec {
   }
 
   "InferWidthsWithAnnos" should "infer widths using WidthGeqConstraintAnnotation" in {
-    val transforms = Seq(
-      ToWorkingIR,
-      CheckHighForm,
-      ResolveKinds,
-      InferTypes,
-      CheckTypes,
-      ResolveFlows,
-      new InferWidths,
-      CheckWidths)
+    val transforms =
+      Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes, ResolveFlows, new InferWidths, CheckWidths)
 
-    val annos = Seq(WidthGeqConstraintAnnotation(
-      ReferenceTarget("Top", "A", Nil, "y", Nil),
-      ReferenceTarget("Top", "B", Nil, "x", Nil)))
+    val annos = Seq(
+      WidthGeqConstraintAnnotation(
+        ReferenceTarget("Top", "A", Nil, "y", Nil),
+        ReferenceTarget("Top", "B", Nil, "x", Nil)
+      )
+    )
 
     val input =
       """circuit Top :
@@ -98,15 +83,8 @@ class InferWidthsWithAnnosSpec extends FirrtlFlatSpec {
   }
 
   "InferWidthsWithAnnos" should "work with token paths" in {
-    val transforms = Seq(
-      ToWorkingIR,
-      CheckHighForm,
-      ResolveKinds,
-      InferTypes,
-      CheckTypes,
-      ResolveFlows,
-      new InferWidths,
-      CheckWidths)
+    val transforms =
+      Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes, ResolveFlows, new InferWidths, CheckWidths)
 
     val tokenLists = Seq(
       Seq(Field("x")),
@@ -117,7 +95,8 @@ class InferWidthsWithAnnosSpec extends FirrtlFlatSpec {
     val annos = tokenLists.map { tokens =>
       WidthGeqConstraintAnnotation(
         ReferenceTarget("Top", "A", Nil, "bundle", tokens),
-        ReferenceTarget("Top", "B", Nil, "bundle", tokens))
+        ReferenceTarget("Top", "B", Nil, "bundle", tokens)
+      )
     }
 
     val input =
@@ -174,7 +153,8 @@ class InferWidthsWithAnnosSpec extends FirrtlFlatSpec {
     val wgeqAnnos = tokenLists.map { tokens =>
       WidthGeqConstraintAnnotation(
         ReferenceTarget("Top", "A", Nil, "bundle", tokens),
-        ReferenceTarget("Top", "B", Nil, "bundle", tokens))
+        ReferenceTarget("Top", "B", Nil, "bundle", tokens)
+      )
     }
 
     val failAnnos = Seq(source, sink)
@@ -209,8 +189,7 @@ class InferWidthsWithAnnosSpec extends FirrtlFlatSpec {
         |  module A :
         |    output bundle_0 : {x : UInt<1>, y: {yy : UInt<3>}[2] }
         |    wire bundle : {x : UInt<1>, y: {yy : UInt<3>}[2] }
-        |    bundle_0 <= bundle"""
-        .stripMargin
+        |    bundle_0 <= bundle""".stripMargin
 
     // should fail without extra constraint annos due to UninferredWidths
     val exceptions = intercept[PassExceptions] {
diff --git a/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala b/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala
index f57586f6..6ee0f5a0 100644
--- a/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala
+++ b/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala
@@ -10,7 +10,7 @@ class LegalizeClocksTransformSpec extends FirrtlFlatSpec {
   def compile(input: String): CircuitState =
     (new MinimumVerilogCompiler).compileAndEmit(CircuitState(parse(input), ChirrtlForm), Nil)
 
-  behavior of "LegalizeClocksTransform"
+  behavior.of("LegalizeClocksTransform")
 
   it should "not emit @(posedge 1'h0) for stop" in {
     val input =
@@ -19,8 +19,8 @@ class LegalizeClocksTransformSpec extends FirrtlFlatSpec {
         |    stop(asClock(UInt(1)), UInt(1), 1)
         |""".stripMargin
     val result = compile(input)
-    result should containLine (s"always @(posedge _GEN_0) begin")
-    result.getEmittedCircuit.value shouldNot include ("always @(posedge 1")
+    result should containLine(s"always @(posedge _GEN_0) begin")
+    result.getEmittedCircuit.value shouldNot include("always @(posedge 1")
   }
 
   it should "not emit @(posedge 1'h0) for printf" in {
@@ -30,8 +30,8 @@ class LegalizeClocksTransformSpec extends FirrtlFlatSpec {
         |    printf(asClock(UInt(1)), UInt(1), "hi")
         |""".stripMargin
     val result = compile(input)
-    result should containLine (s"always @(posedge _GEN_0) begin")
-    result.getEmittedCircuit.value shouldNot include ("always @(posedge 1")
+    result should containLine(s"always @(posedge _GEN_0) begin")
+    result.getEmittedCircuit.value shouldNot include("always @(posedge 1")
   }
 
   it should "not emit @(posedge 1'h0) for reg" in {
@@ -45,8 +45,8 @@ class LegalizeClocksTransformSpec extends FirrtlFlatSpec {
         |    out <= r
         |""".stripMargin
     val result = compile(input)
-    result should containLine (s"always @(posedge _GEN_0) begin")
-    result.getEmittedCircuit.value shouldNot include ("always @(posedge 1")
+    result should containLine(s"always @(posedge _GEN_0) begin")
+    result.getEmittedCircuit.value shouldNot include("always @(posedge 1")
   }
 
   it should "deduplicate injected nodes for literal clocks" in {
@@ -57,11 +57,11 @@ class LegalizeClocksTransformSpec extends FirrtlFlatSpec {
         |    stop(asClock(UInt(1)), UInt(1), 1)
         |""".stripMargin
     val result = compile(input)
-    result should containLine (s"wire  _GEN_0 = 1'h1;")
+    result should containLine(s"wire  _GEN_0 = 1'h1;")
     // Check that there's only 1 _GEN_0 instantiation
     val verilog = result.getEmittedCircuit.value
     val matches = "wire\\s+_GEN_0\\s+=\\s+1'h1".r.findAllIn(verilog)
-    matches.size should be (1)
+    matches.size should be(1)
 
   }
 }
diff --git a/src/test/scala/firrtlTests/transforms/LegalizeReductions.scala b/src/test/scala/firrtlTests/transforms/LegalizeReductions.scala
index 5368c54c..3df47f1d 100644
--- a/src/test/scala/firrtlTests/transforms/LegalizeReductions.scala
+++ b/src/test/scala/firrtlTests/transforms/LegalizeReductions.scala
@@ -12,12 +12,11 @@ import java.io.File
 
 object LegalizeAndReductionsTransformSpec extends FirrtlRunners {
   private case class Test(
-    name: String,
-    op: String,
-    input: BigInt,
-    expected: BigInt,
-    forceWidth: Option[Int] = None
-  ) {
+    name:       String,
+    op:         String,
+    input:      BigInt,
+    expected:   BigInt,
+    forceWidth: Option[Int] = None) {
     def toFirrtl: String = {
       val width = forceWidth.getOrElse(input.bitLength)
       val inputLit = s"""UInt("h${input.toString(16)}")"""
@@ -62,9 +61,9 @@ circuit $name :
     // Run FIRRTL
     val annos =
       FirrtlSourceAnnotation(test.toFirrtl) ::
-      TargetDirAnnotation(testDir.toString) ::
-      CompilerAnnotation(new MinimumVerilogCompiler) ::
-      Nil
+        TargetDirAnnotation(testDir.toString) ::
+        CompilerAnnotation(new MinimumVerilogCompiler) ::
+        Nil
     val resultAnnos = (new FirrtlStage).transform(annos)
     val outputFilename = resultAnnos.collectFirst { case OutputFileAnnotation(f) => f }
     outputFilename.toRight(s"Output file not found!")
@@ -73,8 +72,8 @@ circuit $name :
     copyResourceToFile(cppHarnessResourceName, harness)
     // Run Verilator
     verilogToCpp(prefix, testDir, Nil, harness, suppressVcd = true) #&&
-    cppToExe(prefix, testDir) !
-    loggingProcessLogger
+      cppToExe(prefix, testDir) !
+      loggingProcessLogger
     // Run binary
     if (!executeExpectingSuccess(prefix, testDir)) {
       throw new Exception("Test failed!") with scala.util.control.NoStackTrace
@@ -82,24 +81,23 @@ circuit $name :
   }
 }
 
-
 class LegalizeAndReductionsTransformSpec extends AnyFlatSpec {
 
   import LegalizeAndReductionsTransformSpec._
 
-  behavior of "LegalizeAndReductionsTransform"
+  behavior.of("LegalizeAndReductionsTransform")
 
   private val tests =
     //   name                      primop  input                          expected  width
-    Test("andreduce_ones",         "andr", BigInt("1"*68, 2),             1) ::
-    Test("andreduce_zero",         "andr", 0,                             0, Some(68)) ::
-    Test("orreduce_ones",          "orr",  BigInt("1"*68, 2),             1) ::
-    Test("orreduce_high_one",      "orr",  BigInt("1" + "0"*67, 2),       1) ::
-    Test("orreduce_zero",          "orr",  0,                             0, Some(68)) ::
-    Test("xorreduce_high_one",     "xorr", BigInt("1" + "0"*67, 2),       1) ::
-    Test("xorreduce_high_low_one", "xorr", BigInt("1" + "0"*66 + "1", 2), 0) ::
-    Test("xorreduce_zero",         "xorr", 0,                             0, Some(68)) ::
-    Nil
+    Test("andreduce_ones", "andr", BigInt("1" * 68, 2), 1) ::
+      Test("andreduce_zero", "andr", 0, 0, Some(68)) ::
+      Test("orreduce_ones", "orr", BigInt("1" * 68, 2), 1) ::
+      Test("orreduce_high_one", "orr", BigInt("1" + "0" * 67, 2), 1) ::
+      Test("orreduce_zero", "orr", 0, 0, Some(68)) ::
+      Test("xorreduce_high_one", "xorr", BigInt("1" + "0" * 67, 2), 1) ::
+      Test("xorreduce_high_low_one", "xorr", BigInt("1" + "0" * 66 + "1", 2), 0) ::
+      Test("xorreduce_zero", "xorr", 0, 0, Some(68)) ::
+      Nil
 
   for (test <- tests) {
     it should s"support ${test.name}" in {
diff --git a/src/test/scala/firrtlTests/transforms/ManipulateNamesSpec.scala b/src/test/scala/firrtlTests/transforms/ManipulateNamesSpec.scala
index ec1b505b..a616b4bd 100644
--- a/src/test/scala/firrtlTests/transforms/ManipulateNamesSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/ManipulateNamesSpec.scala
@@ -2,22 +2,15 @@
 
 package firrtlTests.transforms
 
-import firrtl.{
-  ir,
-  CircuitState,
-  FirrtlUserException,
-  Namespace,
-  Parser,
-  RenameMap
-}
+import firrtl.{ir, CircuitState, FirrtlUserException, Namespace, Parser, RenameMap}
 import firrtl.annotations.CircuitTarget
 import firrtl.options.Dependency
 import firrtl.testutils.FirrtlCheckers._
 import firrtl.transforms.{
   ManipulateNames,
-  ManipulateNamesBlocklistAnnotation,
   ManipulateNamesAllowlistAnnotation,
-  ManipulateNamesAllowlistResultAnnotation
+  ManipulateNamesAllowlistResultAnnotation,
+  ManipulateNamesBlocklistAnnotation
 }
 
 import org.scalatest.flatspec.AnyFlatSpec
@@ -57,24 +50,24 @@ class ManipulateNamesSpec extends AnyFlatSpec with Matchers {
     val tm = new firrtl.stage.transforms.Compiler(Seq(Dependency[AddPrefix]))
   }
 
-  behavior of "ManipulateNames"
+  behavior.of("ManipulateNames")
 
   it should "rename everything by default" in new CircuitFixture {
     val state = CircuitState(Parser.parse(input), Seq.empty)
     val statex = tm.execute(state)
     val expected: Seq[PartialFunction[Any, Boolean]] = Seq(
       { case ir.Circuit(_, _, "prefix_Foo") => true },
-      { case ir.Module(_, "prefix_Foo", _, _) => true},
-      { case ir.Module(_, "prefix_Bar", _, _) => true}
+      { case ir.Module(_, "prefix_Foo", _, _) => true },
+      { case ir.Module(_, "prefix_Bar", _, _) => true }
     )
-    expected.foreach(statex should containTree (_))
+    expected.foreach(statex should containTree(_))
   }
 
   it should "do nothing if the circuit is blocklisted" in new CircuitFixture {
     val annotations = Seq(ManipulateNamesBlocklistAnnotation(Seq(Seq(`~Foo`)), Dependency[AddPrefix]))
     val state = CircuitState(Parser.parse(input), annotations)
     val statex = tm.execute(state)
-    state.circuit.serialize should be (statex.circuit.serialize)
+    state.circuit.serialize should be(statex.circuit.serialize)
   }
 
   it should "not rename the circuit if the top module is blocklisted" in new CircuitFixture {
@@ -82,31 +75,31 @@ class ManipulateNamesSpec extends AnyFlatSpec with Matchers {
     val state = CircuitState(Parser.parse(input), annotations)
     val expected: Seq[PartialFunction[Any, Boolean]] = Seq(
       { case ir.Circuit(_, _, "Foo") => true },
-      { case ir.Module(_, "Foo", _, _) => true},
-      { case ir.Module(_, "prefix_Bar", _, _) => true}
+      { case ir.Module(_, "Foo", _, _) => true },
+      { case ir.Module(_, "prefix_Bar", _, _) => true }
     )
     val statex = tm.execute(state)
-    expected.foreach(statex should containTree (_))
+    expected.foreach(statex should containTree(_))
   }
 
   it should "not rename instances if blocklisted" in new CircuitFixture {
     val annotations = Seq(ManipulateNamesBlocklistAnnotation(Seq(Seq(`~Foo|Foo/bar:Bar`)), Dependency[AddPrefix]))
     val state = CircuitState(Parser.parse(input), annotations)
     val expected: Seq[PartialFunction[Any, Boolean]] = Seq(
-      { case ir.DefInstance(_, "bar", "prefix_Bar", _) => true},
-      { case ir.Module(_, "prefix_Bar", _, _) => true}
+      { case ir.DefInstance(_, "bar", "prefix_Bar", _) => true },
+      { case ir.Module(_, "prefix_Bar", _, _) => true }
     )
     val statex = tm.execute(state)
-    expected.foreach(statex should containTree (_))
+    expected.foreach(statex should containTree(_))
   }
 
-  it  should "do nothing if the circuit is not allowlisted" in new CircuitFixture {
+  it should "do nothing if the circuit is not allowlisted" in new CircuitFixture {
     val annotations = Seq(
       ManipulateNamesAllowlistAnnotation(Seq(Seq(`~Foo|Foo`)), Dependency[AddPrefix])
     )
     val state = CircuitState(Parser.parse(input), annotations)
     val statex = tm.execute(state)
-    state.circuit.serialize should be (statex.circuit.serialize)
+    state.circuit.serialize should be(statex.circuit.serialize)
   }
 
   it should "rename only the circuit if allowlisted" in new CircuitFixture {
@@ -118,13 +111,13 @@ class ManipulateNamesSpec extends AnyFlatSpec with Matchers {
     val statex = tm.execute(state)
     val expected: Seq[PartialFunction[Any, Boolean]] = Seq(
       { case ir.Circuit(_, _, "prefix_Foo") => true },
-      { case ir.Module(_, "prefix_Foo", _, _) => true},
-      { case ir.DefInstance(_, "bar", "Bar", _) => true},
-      { case ir.DefInstance(_, "bar2", "Bar", _) => true},
-      { case ir.Module(_, "Bar", _, _) => true},
-      { case ir.DefNode(_, "a", _) => true}
+      { case ir.Module(_, "prefix_Foo", _, _) => true },
+      { case ir.DefInstance(_, "bar", "Bar", _) => true },
+      { case ir.DefInstance(_, "bar2", "Bar", _) => true },
+      { case ir.Module(_, "Bar", _, _) => true },
+      { case ir.DefNode(_, "a", _) => true }
     )
-    expected.foreach(statex should containTree (_))
+    expected.foreach(statex should containTree(_))
   }
 
   it should "rename an instance via allowlisting" in new CircuitFixture {
@@ -136,13 +129,13 @@ class ManipulateNamesSpec extends AnyFlatSpec with Matchers {
     val statex = tm.execute(state)
     val expected: Seq[PartialFunction[Any, Boolean]] = Seq(
       { case ir.Circuit(_, _, "Foo") => true },
-      { case ir.Module(_, "Foo", _, _) => true},
-      { case ir.DefInstance(_, "prefix_bar", "Bar", _) => true},
-      { case ir.DefInstance(_, "bar2", "Bar", _) => true},
-      { case ir.Module(_, "Bar", _, _) => true},
-      { case ir.DefNode(_, "a", _) => true}
+      { case ir.Module(_, "Foo", _, _) => true },
+      { case ir.DefInstance(_, "prefix_bar", "Bar", _) => true },
+      { case ir.DefInstance(_, "bar2", "Bar", _) => true },
+      { case ir.Module(_, "Bar", _, _) => true },
+      { case ir.DefNode(_, "a", _) => true }
     )
-    expected.foreach(statex should containTree (_))
+    expected.foreach(statex should containTree(_))
   }
 
   it should "rename a node via allowlisting" in new CircuitFixture {
@@ -154,13 +147,13 @@ class ManipulateNamesSpec extends AnyFlatSpec with Matchers {
     val statex = tm.execute(state)
     val expected: Seq[PartialFunction[Any, Boolean]] = Seq(
       { case ir.Circuit(_, _, "Foo") => true },
-      { case ir.Module(_, "Foo", _, _) => true},
-      { case ir.DefInstance(_, "bar", "Bar", _) => true},
-      { case ir.DefInstance(_, "bar2", "Bar", _) => true},
-      { case ir.Module(_, "Bar", _, _) => true},
-      { case ir.DefNode(_, "prefix_a", _) => true}
+      { case ir.Module(_, "Foo", _, _) => true },
+      { case ir.DefInstance(_, "bar", "Bar", _) => true },
+      { case ir.DefInstance(_, "bar2", "Bar", _) => true },
+      { case ir.Module(_, "Bar", _, _) => true },
+      { case ir.DefNode(_, "prefix_a", _) => true }
     )
-    expected.foreach(statex should containTree (_))
+    expected.foreach(statex should containTree(_))
   }
 
   it should "throw user errors on circuits that haven't been run through LowerTypes" in {
@@ -171,9 +164,9 @@ class ManipulateNamesSpec extends AnyFlatSpec with Matchers {
          |    node baz = bar.a
          |""".stripMargin
     val state = CircuitState(Parser.parse(input), Seq.empty)
-    intercept [FirrtlUserException] {
+    intercept[FirrtlUserException] {
       (new AddPrefix).transform(state)
-    }.getMessage should include ("LowerTypes")
+    }.getMessage should include("LowerTypes")
   }
 
   it should "only consume annotations whose type parameter matches" in new CircuitFixture {
@@ -187,25 +180,25 @@ class ManipulateNamesSpec extends AnyFlatSpec with Matchers {
     val statex = tm.execute(state)
     val expected: Seq[PartialFunction[Any, Boolean]] = Seq(
       { case ir.Circuit(_, _, "prefix_Foo") => true },
-      { case ir.Module(_, "prefix_Foo", _, _) => true},
-      { case ir.DefInstance(_, "prefix_bar", "prefix_Bar", _) => true},
-      { case ir.DefInstance(_, "prefix_bar2", "prefix_Bar", _) => true},
-      { case ir.Module(_, "prefix_Bar", _, _) => true},
-      { case ir.DefNode(_, "a_suffix", _) => true}
+      { case ir.Module(_, "prefix_Foo", _, _) => true },
+      { case ir.DefInstance(_, "prefix_bar", "prefix_Bar", _) => true },
+      { case ir.DefInstance(_, "prefix_bar2", "prefix_Bar", _) => true },
+      { case ir.Module(_, "prefix_Bar", _, _) => true },
+      { case ir.DefNode(_, "a_suffix", _) => true }
     )
-    expected.foreach(statex should containTree (_))
+    expected.foreach(statex should containTree(_))
   }
 
-  behavior of "ManipulateNamesBlocklistAnnotation"
+  behavior.of("ManipulateNamesBlocklistAnnotation")
 
   it should "throw an exception if a non-local target is skipped" in new CircuitFixture {
     val barA = CircuitTarget("Foo").module("Foo").instOf("bar", "Bar").ref("a")
-    assertThrows[java.lang.IllegalArgumentException]{
+    assertThrows[java.lang.IllegalArgumentException] {
       Seq(ManipulateNamesBlocklistAnnotation(Seq(Seq(barA)), Dependency[AddPrefix]))
     }
   }
 
-  behavior of "ManipulateNamesAllowlistResultAnnotation"
+  behavior.of("ManipulateNamesAllowlistResultAnnotation")
 
   it should "delete itself if the new target is deleted" in {
     val `~Foo|Bar` = CircuitTarget("Foo").module("Bar")
@@ -220,7 +213,7 @@ class ManipulateNamesSpec extends AnyFlatSpec with Matchers {
     val r = RenameMap()
     r.delete(`~Foo|prefix_Bar`)
 
-    a.update(r) should be (empty)
+    a.update(r) should be(empty)
   }
 
   it should "drop a deleted target" in {
@@ -242,12 +235,12 @@ class ManipulateNamesSpec extends AnyFlatSpec with Matchers {
       case b: ManipulateNamesAllowlistResultAnnotation[_] => b
     }
 
-    ax should not be length (1)
+    ax should not be length(1)
 
     val keys = ax.head.toRenameMap.getUnderlying.keys
 
     keys should not contain (`~Foo|Bar`)
-    keys should contain (`~Foo|Baz`)
+    keys should contain(`~Foo|Baz`)
   }
 
 }
diff --git a/src/test/scala/firrtlTests/transforms/RemoveResetSpec.scala b/src/test/scala/firrtlTests/transforms/RemoveResetSpec.scala
index 299a4f48..d603db69 100644
--- a/src/test/scala/firrtlTests/transforms/RemoveResetSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/RemoveResetSpec.scala
@@ -8,7 +8,7 @@ import firrtl.testutils.FirrtlFlatSpec
 import firrtl.testutils.FirrtlCheckers._
 
 import firrtl.{CircuitState, WRef}
-import firrtl.ir.{Connect, Mux, DefRegister}
+import firrtl.ir.{Connect, DefRegister, Mux}
 import firrtl.stage.{FirrtlCircuitAnnotation, FirrtlSourceAnnotation, FirrtlStage}
 
 class RemoveResetSpec extends FirrtlFlatSpec with GivenWhenThen {
@@ -17,12 +17,12 @@ class RemoveResetSpec extends FirrtlFlatSpec with GivenWhenThen {
     When("the circuit is compiled to low FIRRTL")
     (new FirrtlStage)
       .execute(Array("-X", "low"), Seq(FirrtlSourceAnnotation(string)))
-      .collectFirst{ case FirrtlCircuitAnnotation(a) => a }
+      .collectFirst { case FirrtlCircuitAnnotation(a) => a }
       .map(a => firrtl.CircuitState(a, firrtl.UnknownForm))
       .get
   }
 
-  behavior of "RemoveReset"
+  behavior.of("RemoveReset")
 
   it should "not generate a reset mux for an invalid init" in {
     Given("a 1-bit register 'foo' initialized to invalid, 1-bit wire 'bar'")
@@ -44,7 +44,7 @@ class RemoveResetSpec extends FirrtlFlatSpec with GivenWhenThen {
     val outputState = toLowFirrtl(input)
 
     Then("'foo' is NOT connected to a reset mux")
-    outputState shouldNot containTree { case Connect(_, WRef("foo",_,_,_), Mux(_,_,_,_)) => true }
+    outputState shouldNot containTree { case Connect(_, WRef("foo", _, _, _), Mux(_, _, _, _)) => true }
   }
 
   it should "generate a reset mux for only the portion of an invalid aggregate that is reset" in {
@@ -71,11 +71,11 @@ class RemoveResetSpec extends FirrtlFlatSpec with GivenWhenThen {
     val outputState = toLowFirrtl(input)
 
     Then("foo.a[0] is NOT connected to a reset mux")
-    outputState shouldNot containTree { case Connect(_, WRef("foo_a_0",_,_,_), Mux(_,_,_,_)) => true }
+    outputState shouldNot containTree { case Connect(_, WRef("foo_a_0", _, _, _), Mux(_, _, _, _)) => true }
     And("foo.a[1] is connected to a reset mux")
-    outputState should    containTree { case Connect(_, WRef("foo_a_1",_,_,_), Mux(_,_,_,_)) => true }
+    outputState should containTree { case Connect(_, WRef("foo_a_1", _, _, _), Mux(_, _, _, _)) => true }
     And("foo.b is NOT connected to a reset mux")
-    outputState shouldNot containTree { case Connect(_, WRef("foo_b",_,_,_),   Mux(_,_,_,_)) => true }
+    outputState shouldNot containTree { case Connect(_, WRef("foo_b", _, _, _), Mux(_, _, _, _)) => true }
   }
 
   it should "propagate invalidations across connects" in {
@@ -107,9 +107,9 @@ class RemoveResetSpec extends FirrtlFlatSpec with GivenWhenThen {
     val outputState = toLowFirrtl(input)
 
     Then("'foo.a' is connected to a reset mux")
-    outputState should    containTree { case Connect(_, WRef("foo_a",_,_,_), Mux(_,_,_,_)) => true }
+    outputState should containTree { case Connect(_, WRef("foo_a", _, _, _), Mux(_, _, _, _)) => true }
     And("'foo.b' is NOT connected to a reset mux")
-    outputState shouldNot containTree { case Connect(_, WRef("foo_b",_,_,_), Mux(_,_,_,_)) => true }
+    outputState shouldNot containTree { case Connect(_, WRef("foo_b", _, _, _), Mux(_, _, _, _)) => true }
   }
 
   it should "canvert a reset wired to UInt<0> to a canonical non-reset" in {
@@ -128,8 +128,8 @@ class RemoveResetSpec extends FirrtlFlatSpec with GivenWhenThen {
     val outputState = toLowFirrtl(input)
 
     Then("foo has a canonical non-reset declaration after RemoveReset")
-    outputState should containTree { case DefRegister(_, "foo", _,_, firrtl.Utils.zero, WRef("foo", _,_,_)) => true }
+    outputState should containTree { case DefRegister(_, "foo", _, _, firrtl.Utils.zero, WRef("foo", _, _, _)) => true }
     And("foo is NOT connected to a reset mux")
-    outputState shouldNot containTree { case Connect(_, WRef("foo",_,_,_), Mux(_,_,_,_)) => true }
+    outputState shouldNot containTree { case Connect(_, WRef("foo", _, _, _), Mux(_, _, _, _)) => true }
   }
 }
diff --git a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
index 0ac12ef8..97fafe41 100644
--- a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
+++ b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
@@ -6,724 +6,718 @@ package transforms
 import java.io._
 
 import firrtl._
-import firrtl.ir.{Type, GroundType, IntWidth}
+import firrtl.ir.{GroundType, IntWidth, Type}
 import firrtl.Parser
-import firrtl.annotations.{
-   CircuitName,
-   ModuleName,
-   ComponentName,
-   Target
-}
+import firrtl.annotations.{CircuitName, ComponentName, ModuleName, Target}
 import firrtl.transforms.TopWiring._
 import firrtl.testutils._
 
-
 trait TopWiringTestsCommon extends FirrtlRunners {
 
-   val testDir = createTestDirectory("TopWiringTests")
-   val testDirName = testDir.getPath
-   def transform = new TopWiringTransform
+  val testDir = createTestDirectory("TopWiringTests")
+  val testDirName = testDir.getPath
+  def transform = new TopWiringTransform
 
-   def topWiringDummyOutputFilesFunction(dir: String,
-                                         mapping: Seq[((ComponentName, Type, Boolean, Seq[String], String), Int)],
-                                         state: CircuitState): CircuitState = {
-     state
-   }
+  def topWiringDummyOutputFilesFunction(
+    dir:     String,
+    mapping: Seq[((ComponentName, Type, Boolean, Seq[String], String), Int)],
+    state:   CircuitState
+  ): CircuitState = {
+    state
+  }
 
-   def topWiringTestOutputFilesFunction(dir: String,
-                                        mapping: Seq[((ComponentName, Type, Boolean, Seq[String], String), Int)],
-                                        state: CircuitState): CircuitState = {
-     val testOutputFile = new PrintWriter(new File(dir, "TopWiringOutputTest.txt" ))
-     mapping map {
-          case ((_, tpe, _, path, prefix), index) => {
-            val portwidth = tpe match { case GroundType(IntWidth(w)) => w }
-            val portnum = index
-            val portname = prefix + path.mkString("_")
-            testOutputFile.append(s"new top level port $portnum : $portname, with width $portwidth \n")
-          }
-     }
-     testOutputFile.close()
-     state
-   }
+  def topWiringTestOutputFilesFunction(
+    dir:     String,
+    mapping: Seq[((ComponentName, Type, Boolean, Seq[String], String), Int)],
+    state:   CircuitState
+  ): CircuitState = {
+    val testOutputFile = new PrintWriter(new File(dir, "TopWiringOutputTest.txt"))
+    mapping.map {
+      case ((_, tpe, _, path, prefix), index) => {
+        val portwidth = tpe match { case GroundType(IntWidth(w)) => w }
+        val portnum = index
+        val portname = prefix + path.mkString("_")
+        testOutputFile.append(s"new top level port $portnum : $portname, with width $portwidth \n")
+      }
+    }
+    testOutputFile.close()
+    state
+  }
 }
 
 /**
- * Tests TopWiring transformation
- */
-class TopWiringTests extends MiddleTransformSpec with TopWiringTestsCommon  {
+  * Tests TopWiring transformation
+  */
+class TopWiringTests extends MiddleTransformSpec with TopWiringTestsCommon {
 
-   "The signal x in module C" should s"be connected to Top port with topwiring prefix and outputfile in $testDirName" in {
-      val input =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |    inst a2 of A_
-           |  module A :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |    inst b1 of B
-           |  module A_ :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |  module B :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |    inst c1 of C
-           |  module C:
-           |    output x: UInt<1>
-           |    x <= UInt(0)
+  "The signal x in module C" should s"be connected to Top port with topwiring prefix and outputfile in $testDirName" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |    inst b1 of B
+        |  module A_ :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |  module B :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |    inst c1 of C
+        |  module C:
+        |    output x: UInt<1>
+        |    x <= UInt(0)
            """.stripMargin
-      val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"x",
-                                                                 ModuleName(s"C", CircuitName(s"Top"))),
-                                                   s"topwiring_"),
-                         TopWiringOutputFilesAnnotation(testDirName, topWiringTestOutputFilesFunction))
-      val check =
-         """circuit Top :
-           |  module Top :
-           |    output topwiring_a1_b1_c1_x: UInt<1>
-           |    inst a1 of A
-           |    inst a2 of A_
-           |    topwiring_a1_b1_c1_x <= a1.topwiring_b1_c1_x
-           |  module A :
-           |    output x: UInt<1>
-           |    output topwiring_b1_c1_x: UInt<1>
-           |    inst b1 of B
-           |    x <= UInt(1)
-           |    topwiring_b1_c1_x <= b1.topwiring_c1_x
-           |  module A_ :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |  module B :
-           |    output x: UInt<1>
-           |    output topwiring_c1_x: UInt<1>
-           |    inst c1 of C
-           |    x <= UInt(1)
-           |    topwiring_c1_x <= c1.topwiring_x
-           |  module C:
-           |    output x: UInt<1>
-           |    output topwiring_x: UInt<1>
-           |    x <= UInt(0)
-           |    topwiring_x <= x
+    val topwiringannos = Seq(
+      TopWiringAnnotation(ComponentName(s"x", ModuleName(s"C", CircuitName(s"Top"))), s"topwiring_"),
+      TopWiringOutputFilesAnnotation(testDirName, topWiringTestOutputFilesFunction)
+    )
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    output topwiring_a1_b1_c1_x: UInt<1>
+        |    inst a1 of A
+        |    inst a2 of A_
+        |    topwiring_a1_b1_c1_x <= a1.topwiring_b1_c1_x
+        |  module A :
+        |    output x: UInt<1>
+        |    output topwiring_b1_c1_x: UInt<1>
+        |    inst b1 of B
+        |    x <= UInt(1)
+        |    topwiring_b1_c1_x <= b1.topwiring_c1_x
+        |  module A_ :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |  module B :
+        |    output x: UInt<1>
+        |    output topwiring_c1_x: UInt<1>
+        |    inst c1 of C
+        |    x <= UInt(1)
+        |    topwiring_c1_x <= c1.topwiring_x
+        |  module C:
+        |    output x: UInt<1>
+        |    output topwiring_x: UInt<1>
+        |    x <= UInt(0)
+        |    topwiring_x <= x
            """.stripMargin
-      execute(input, check, topwiringannos)
-   }
+    execute(input, check, topwiringannos)
+  }
 
-   "The signal x in module C inst c1 and c2" should
+  "The signal x in module C inst c1 and c2" should
     s"be connected to Top port with topwiring prefix and outfile in $testDirName" in {
-      val input =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |    inst a2 of A_
-           |  module A :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |    inst b1 of B
-           |  module A_ :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |  module B :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |    inst c1 of C
-           |    inst c2 of C
-           |  module C:
-           |    output x: UInt<1>
-           |    x <= UInt(0)
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |    inst b1 of B
+        |  module A_ :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |  module B :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |    inst c1 of C
+        |    inst c2 of C
+        |  module C:
+        |    output x: UInt<1>
+        |    x <= UInt(0)
            """.stripMargin
-      val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"x",
-                                                    ModuleName(s"C", CircuitName(s"Top"))), s"topwiring_"),
-                               TopWiringOutputFilesAnnotation(testDirName, topWiringTestOutputFilesFunction))
-      val check =
-         """circuit Top :
-           |  module Top :
-           |    output topwiring_a1_b1_c1_x: UInt<1>
-           |    output topwiring_a1_b1_c2_x: UInt<1>
-           |    inst a1 of A
-           |    inst a2 of A_
-           |    topwiring_a1_b1_c1_x <= a1.topwiring_b1_c1_x
-           |    topwiring_a1_b1_c2_x <= a1.topwiring_b1_c2_x
-           |  module A :
-           |    output x: UInt<1>
-           |    output topwiring_b1_c1_x: UInt<1>
-           |    output topwiring_b1_c2_x: UInt<1>
-           |    inst b1 of B
-           |    x <= UInt(1)
-           |    topwiring_b1_c1_x <= b1.topwiring_c1_x
-           |    topwiring_b1_c2_x <= b1.topwiring_c2_x
-           |  module A_ :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |  module B :
-           |    output x: UInt<1>
-           |    output topwiring_c1_x: UInt<1>
-           |    output topwiring_c2_x: UInt<1>
-           |    inst c1 of C
-           |    inst c2 of C
-           |    x <= UInt(1)
-           |    topwiring_c1_x <= c1.topwiring_x
-           |    topwiring_c2_x <= c2.topwiring_x
-           |  module C:
-           |    output x: UInt<1>
-           |    output topwiring_x: UInt<1>
-           |    x <= UInt(0)
-           |    topwiring_x <= x
+    val topwiringannos = Seq(
+      TopWiringAnnotation(ComponentName(s"x", ModuleName(s"C", CircuitName(s"Top"))), s"topwiring_"),
+      TopWiringOutputFilesAnnotation(testDirName, topWiringTestOutputFilesFunction)
+    )
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    output topwiring_a1_b1_c1_x: UInt<1>
+        |    output topwiring_a1_b1_c2_x: UInt<1>
+        |    inst a1 of A
+        |    inst a2 of A_
+        |    topwiring_a1_b1_c1_x <= a1.topwiring_b1_c1_x
+        |    topwiring_a1_b1_c2_x <= a1.topwiring_b1_c2_x
+        |  module A :
+        |    output x: UInt<1>
+        |    output topwiring_b1_c1_x: UInt<1>
+        |    output topwiring_b1_c2_x: UInt<1>
+        |    inst b1 of B
+        |    x <= UInt(1)
+        |    topwiring_b1_c1_x <= b1.topwiring_c1_x
+        |    topwiring_b1_c2_x <= b1.topwiring_c2_x
+        |  module A_ :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |  module B :
+        |    output x: UInt<1>
+        |    output topwiring_c1_x: UInt<1>
+        |    output topwiring_c2_x: UInt<1>
+        |    inst c1 of C
+        |    inst c2 of C
+        |    x <= UInt(1)
+        |    topwiring_c1_x <= c1.topwiring_x
+        |    topwiring_c2_x <= c2.topwiring_x
+        |  module C:
+        |    output x: UInt<1>
+        |    output topwiring_x: UInt<1>
+        |    x <= UInt(0)
+        |    topwiring_x <= x
            """.stripMargin
-      execute(input, check, topwiringannos)
-   }
+    execute(input, check, topwiringannos)
+  }
 
-   "The signal x in module C" should
-   s"be connected to Top port with topwiring prefix and outputfile in $testDirName, after name colission" in {
-      val input =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |    inst a2 of A_
-           |    wire topwiring_a1_b1_c1_x : UInt<1>
-           |    topwiring_a1_b1_c1_x <= UInt(0)
-           |  module A :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |    inst b1 of B
-           |    wire topwiring_b1_c1_x : UInt<1>
-           |    topwiring_b1_c1_x <= UInt(0)
-           |  module A_ :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |  module B :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |    inst c1 of C
-           |  module C:
-           |    output x: UInt<1>
-           |    x <= UInt(0)
+  "The signal x in module C" should
+    s"be connected to Top port with topwiring prefix and outputfile in $testDirName, after name colission" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |    wire topwiring_a1_b1_c1_x : UInt<1>
+        |    topwiring_a1_b1_c1_x <= UInt(0)
+        |  module A :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |    inst b1 of B
+        |    wire topwiring_b1_c1_x : UInt<1>
+        |    topwiring_b1_c1_x <= UInt(0)
+        |  module A_ :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |  module B :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |    inst c1 of C
+        |  module C:
+        |    output x: UInt<1>
+        |    x <= UInt(0)
            """.stripMargin
-      val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"x",
-                                                                 ModuleName(s"C", CircuitName(s"Top"))),
-                                                                 s"topwiring_"),
-                               TopWiringOutputFilesAnnotation(testDirName, topWiringTestOutputFilesFunction))
-      val check =
-         """circuit Top :
-           |  module Top :
-           |    output topwiring_a1_b1_c1_x_0: UInt<1>
-           |    inst a1 of A
-           |    inst a2 of A_
-           |    wire topwiring_a1_b1_c1_x : UInt<1>
-           |    topwiring_a1_b1_c1_x <= UInt<1>("h0")
-           |    topwiring_a1_b1_c1_x_0 <= a1.topwiring_b1_c1_x_0
-           |  module A :
-           |    output x: UInt<1>
-           |    output topwiring_b1_c1_x_0: UInt<1>
-           |    inst b1 of B
-           |    wire topwiring_b1_c1_x : UInt<1>
-           |    x <= UInt(1)
-           |    topwiring_b1_c1_x <= UInt<1>("h0")
-           |    topwiring_b1_c1_x_0 <= b1.topwiring_c1_x
-           |  module A_ :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |  module B :
-           |    output x: UInt<1>
-           |    output topwiring_c1_x: UInt<1>
-           |    inst c1 of C
-           |    x <= UInt(1)
-           |    topwiring_c1_x <= c1.topwiring_x
-           |  module C:
-           |    output x: UInt<1>
-           |    output topwiring_x: UInt<1>
-           |    x <= UInt(0)
-           |    topwiring_x <= x
+    val topwiringannos = Seq(
+      TopWiringAnnotation(ComponentName(s"x", ModuleName(s"C", CircuitName(s"Top"))), s"topwiring_"),
+      TopWiringOutputFilesAnnotation(testDirName, topWiringTestOutputFilesFunction)
+    )
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    output topwiring_a1_b1_c1_x_0: UInt<1>
+        |    inst a1 of A
+        |    inst a2 of A_
+        |    wire topwiring_a1_b1_c1_x : UInt<1>
+        |    topwiring_a1_b1_c1_x <= UInt<1>("h0")
+        |    topwiring_a1_b1_c1_x_0 <= a1.topwiring_b1_c1_x_0
+        |  module A :
+        |    output x: UInt<1>
+        |    output topwiring_b1_c1_x_0: UInt<1>
+        |    inst b1 of B
+        |    wire topwiring_b1_c1_x : UInt<1>
+        |    x <= UInt(1)
+        |    topwiring_b1_c1_x <= UInt<1>("h0")
+        |    topwiring_b1_c1_x_0 <= b1.topwiring_c1_x
+        |  module A_ :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |  module B :
+        |    output x: UInt<1>
+        |    output topwiring_c1_x: UInt<1>
+        |    inst c1 of C
+        |    x <= UInt(1)
+        |    topwiring_c1_x <= c1.topwiring_x
+        |  module C:
+        |    output x: UInt<1>
+        |    output topwiring_x: UInt<1>
+        |    x <= UInt(0)
+        |    topwiring_x <= x
            """.stripMargin
-      execute(input, check, topwiringannos)
-   }
+    execute(input, check, topwiringannos)
+  }
 
-   "The signal x in module C" should
-   "be connected to Top port with topwiring prefix and no output function" in {
-      val input =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |    inst a2 of A_
-           |  module A :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |    inst b1 of B
-           |  module A_ :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |  module B :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |    inst c1 of C
-           |  module C:
-           |    output x: UInt<1>
-           |    x <= UInt(0)
+  "The signal x in module C" should
+    "be connected to Top port with topwiring prefix and no output function" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |    inst b1 of B
+        |  module A_ :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |  module B :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |    inst c1 of C
+        |  module C:
+        |    output x: UInt<1>
+        |    x <= UInt(0)
            """.stripMargin
-      val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"x",
-                                                                 ModuleName(s"C", CircuitName(s"Top"))),
-                                                   s"topwiring_"))
-      val check =
-         """circuit Top :
-           |  module Top :
-           |    output topwiring_a1_b1_c1_x: UInt<1>
-           |    inst a1 of A
-           |    inst a2 of A_
-           |    topwiring_a1_b1_c1_x <= a1.topwiring_b1_c1_x
-           |  module A :
-           |    output x: UInt<1>
-           |    output topwiring_b1_c1_x: UInt<1>
-           |    inst b1 of B
-           |    x <= UInt(1)
-           |    topwiring_b1_c1_x <= b1.topwiring_c1_x
-           |  module A_ :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |  module B :
-           |    output x: UInt<1>
-           |    output topwiring_c1_x: UInt<1>
-           |    inst c1 of C
-           |    x <= UInt(1)
-           |    topwiring_c1_x <= c1.topwiring_x
-           |  module C:
-           |    output x: UInt<1>
-           |    output topwiring_x: UInt<1>
-           |    x <= UInt(0)
-           |    topwiring_x <= x
+    val topwiringannos =
+      Seq(TopWiringAnnotation(ComponentName(s"x", ModuleName(s"C", CircuitName(s"Top"))), s"topwiring_"))
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    output topwiring_a1_b1_c1_x: UInt<1>
+        |    inst a1 of A
+        |    inst a2 of A_
+        |    topwiring_a1_b1_c1_x <= a1.topwiring_b1_c1_x
+        |  module A :
+        |    output x: UInt<1>
+        |    output topwiring_b1_c1_x: UInt<1>
+        |    inst b1 of B
+        |    x <= UInt(1)
+        |    topwiring_b1_c1_x <= b1.topwiring_c1_x
+        |  module A_ :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |  module B :
+        |    output x: UInt<1>
+        |    output topwiring_c1_x: UInt<1>
+        |    inst c1 of C
+        |    x <= UInt(1)
+        |    topwiring_c1_x <= c1.topwiring_x
+        |  module C:
+        |    output x: UInt<1>
+        |    output topwiring_x: UInt<1>
+        |    x <= UInt(0)
+        |    topwiring_x <= x
            """.stripMargin
-      execute(input, check, topwiringannos)
-   }
+    execute(input, check, topwiringannos)
+  }
 
-   "The signal x in module C inst c1 and c2 and signal y in module A_" should
-   s"be connected to Top port with topwiring prefix and outfile in $testDirName" in {
-      val input =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |    inst a2 of A_
-           |  module A :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |    inst b1 of B
-           |  module A_ :
-           |    output x: UInt<1>
-           |    wire y : UInt<1>
-           |    y <= UInt(1)
-           |    x <= UInt(1)
-           |  module B :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |    inst c1 of C
-           |    inst c2 of C
-           |  module C:
-           |    output x: UInt<1>
-           |    x <= UInt(0)
+  "The signal x in module C inst c1 and c2 and signal y in module A_" should
+    s"be connected to Top port with topwiring prefix and outfile in $testDirName" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |    inst b1 of B
+        |  module A_ :
+        |    output x: UInt<1>
+        |    wire y : UInt<1>
+        |    y <= UInt(1)
+        |    x <= UInt(1)
+        |  module B :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |    inst c1 of C
+        |    inst c2 of C
+        |  module C:
+        |    output x: UInt<1>
+        |    x <= UInt(0)
            """.stripMargin
-      val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"x",
-                                                                 ModuleName(s"C", CircuitName(s"Top"))),
-                                                   s"topwiring_"),
-                               TopWiringAnnotation(ComponentName(s"y",
-                                                                 ModuleName(s"A_", CircuitName(s"Top"))),
-                                                   s"topwiring_"),
-                         TopWiringOutputFilesAnnotation(testDirName, topWiringTestOutputFilesFunction))
-      val check =
-         """circuit Top :
-           |  module Top :
-           |    output topwiring_a1_b1_c1_x: UInt<1>
-           |    output topwiring_a1_b1_c2_x: UInt<1>
-           |    output topwiring_a2_y: UInt<1>
-           |    inst a1 of A
-           |    inst a2 of A_
-           |    topwiring_a1_b1_c1_x <= a1.topwiring_b1_c1_x
-           |    topwiring_a1_b1_c2_x <= a1.topwiring_b1_c2_x
-           |    topwiring_a2_y <= a2.topwiring_y
-           |  module A :
-           |    output x: UInt<1>
-           |    output topwiring_b1_c1_x: UInt<1>
-           |    output topwiring_b1_c2_x: UInt<1>
-           |    inst b1 of B
-           |    x <= UInt(1)
-           |    topwiring_b1_c1_x <= b1.topwiring_c1_x
-           |    topwiring_b1_c2_x <= b1.topwiring_c2_x
-           |  module A_ :
-           |    output x: UInt<1>
-           |    output topwiring_y: UInt<1>
-           |    wire y : UInt<1>
-           |    x <= UInt(1)
-           |    y <= UInt<1>("h1")
-           |    topwiring_y <= y
-           |  module B :
-           |    output x: UInt<1>
-           |    output topwiring_c1_x: UInt<1>
-           |    output topwiring_c2_x: UInt<1>
-           |    inst c1 of C
-           |    inst c2 of C
-           |    x <= UInt(1)
-           |    topwiring_c1_x <= c1.topwiring_x
-           |    topwiring_c2_x <= c2.topwiring_x
-           |  module C:
-           |    output x: UInt<1>
-           |    output topwiring_x: UInt<1>
-           |    x <= UInt(0)
-           |    topwiring_x <= x
+    val topwiringannos = Seq(
+      TopWiringAnnotation(ComponentName(s"x", ModuleName(s"C", CircuitName(s"Top"))), s"topwiring_"),
+      TopWiringAnnotation(ComponentName(s"y", ModuleName(s"A_", CircuitName(s"Top"))), s"topwiring_"),
+      TopWiringOutputFilesAnnotation(testDirName, topWiringTestOutputFilesFunction)
+    )
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    output topwiring_a1_b1_c1_x: UInt<1>
+        |    output topwiring_a1_b1_c2_x: UInt<1>
+        |    output topwiring_a2_y: UInt<1>
+        |    inst a1 of A
+        |    inst a2 of A_
+        |    topwiring_a1_b1_c1_x <= a1.topwiring_b1_c1_x
+        |    topwiring_a1_b1_c2_x <= a1.topwiring_b1_c2_x
+        |    topwiring_a2_y <= a2.topwiring_y
+        |  module A :
+        |    output x: UInt<1>
+        |    output topwiring_b1_c1_x: UInt<1>
+        |    output topwiring_b1_c2_x: UInt<1>
+        |    inst b1 of B
+        |    x <= UInt(1)
+        |    topwiring_b1_c1_x <= b1.topwiring_c1_x
+        |    topwiring_b1_c2_x <= b1.topwiring_c2_x
+        |  module A_ :
+        |    output x: UInt<1>
+        |    output topwiring_y: UInt<1>
+        |    wire y : UInt<1>
+        |    x <= UInt(1)
+        |    y <= UInt<1>("h1")
+        |    topwiring_y <= y
+        |  module B :
+        |    output x: UInt<1>
+        |    output topwiring_c1_x: UInt<1>
+        |    output topwiring_c2_x: UInt<1>
+        |    inst c1 of C
+        |    inst c2 of C
+        |    x <= UInt(1)
+        |    topwiring_c1_x <= c1.topwiring_x
+        |    topwiring_c2_x <= c2.topwiring_x
+        |  module C:
+        |    output x: UInt<1>
+        |    output topwiring_x: UInt<1>
+        |    x <= UInt(0)
+        |    topwiring_x <= x
            """.stripMargin
-      execute(input, check, topwiringannos)
-   }
+    execute(input, check, topwiringannos)
+  }
 
-   "The signal x in module C inst c1 and c2 and signal y in module A_" should
-   s"be connected to Top port with topwiring and top2wiring prefix and outfile in $testDirName" in {
-      val input =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |    inst a2 of A_
-           |  module A :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |    inst b1 of B
-           |  module A_ :
-           |    output x: UInt<1>
-           |    wire y : UInt<1>
-           |    y <= UInt(1)
-           |    x <= UInt(1)
-           |  module B :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |    inst c1 of C
-           |    inst c2 of C
-           |  module C:
-           |    output x: UInt<1>
-           |    x <= UInt(0)
+  "The signal x in module C inst c1 and c2 and signal y in module A_" should
+    s"be connected to Top port with topwiring and top2wiring prefix and outfile in $testDirName" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |    inst b1 of B
+        |  module A_ :
+        |    output x: UInt<1>
+        |    wire y : UInt<1>
+        |    y <= UInt(1)
+        |    x <= UInt(1)
+        |  module B :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |    inst c1 of C
+        |    inst c2 of C
+        |  module C:
+        |    output x: UInt<1>
+        |    x <= UInt(0)
            """.stripMargin
-      val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"x",
-                                                                 ModuleName(s"C", CircuitName(s"Top"))),
-                                                   s"topwiring_"),
-                               TopWiringAnnotation(ComponentName(s"y",
-                                                                 ModuleName(s"A_", CircuitName(s"Top"))),
-                                                   s"top2wiring_"),
-                         TopWiringOutputFilesAnnotation(testDirName, topWiringTestOutputFilesFunction))
-      val check =
-         """circuit Top :
-           |  module Top :
-           |    output topwiring_a1_b1_c1_x: UInt<1>
-           |    output topwiring_a1_b1_c2_x: UInt<1>
-           |    output top2wiring_a2_y: UInt<1>
-           |    inst a1 of A
-           |    inst a2 of A_
-           |    topwiring_a1_b1_c1_x <= a1.topwiring_b1_c1_x
-           |    topwiring_a1_b1_c2_x <= a1.topwiring_b1_c2_x
-           |    top2wiring_a2_y <= a2.top2wiring_y
-           |  module A :
-           |    output x: UInt<1>
-           |    output topwiring_b1_c1_x: UInt<1>
-           |    output topwiring_b1_c2_x: UInt<1>
-           |    inst b1 of B
-           |    x <= UInt(1)
-           |    topwiring_b1_c1_x <= b1.topwiring_c1_x
-           |    topwiring_b1_c2_x <= b1.topwiring_c2_x
-           |  module A_ :
-           |    output x: UInt<1>
-           |    output top2wiring_y: UInt<1>
-           |    wire y : UInt<1>
-           |    x <= UInt(1)
-           |    y <= UInt<1>("h1")
-           |    top2wiring_y <= y
-           |  module B :
-           |    output x: UInt<1>
-           |    output topwiring_c1_x: UInt<1>
-           |    output topwiring_c2_x: UInt<1>
-           |    inst c1 of C
-           |    inst c2 of C
-           |    x <= UInt(1)
-           |    topwiring_c1_x <= c1.topwiring_x
-           |    topwiring_c2_x <= c2.topwiring_x
-           |  module C:
-           |    output x: UInt<1>
-           |    output topwiring_x: UInt<1>
-           |    x <= UInt(0)
-           |    topwiring_x <= x
+    val topwiringannos = Seq(
+      TopWiringAnnotation(ComponentName(s"x", ModuleName(s"C", CircuitName(s"Top"))), s"topwiring_"),
+      TopWiringAnnotation(ComponentName(s"y", ModuleName(s"A_", CircuitName(s"Top"))), s"top2wiring_"),
+      TopWiringOutputFilesAnnotation(testDirName, topWiringTestOutputFilesFunction)
+    )
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    output topwiring_a1_b1_c1_x: UInt<1>
+        |    output topwiring_a1_b1_c2_x: UInt<1>
+        |    output top2wiring_a2_y: UInt<1>
+        |    inst a1 of A
+        |    inst a2 of A_
+        |    topwiring_a1_b1_c1_x <= a1.topwiring_b1_c1_x
+        |    topwiring_a1_b1_c2_x <= a1.topwiring_b1_c2_x
+        |    top2wiring_a2_y <= a2.top2wiring_y
+        |  module A :
+        |    output x: UInt<1>
+        |    output topwiring_b1_c1_x: UInt<1>
+        |    output topwiring_b1_c2_x: UInt<1>
+        |    inst b1 of B
+        |    x <= UInt(1)
+        |    topwiring_b1_c1_x <= b1.topwiring_c1_x
+        |    topwiring_b1_c2_x <= b1.topwiring_c2_x
+        |  module A_ :
+        |    output x: UInt<1>
+        |    output top2wiring_y: UInt<1>
+        |    wire y : UInt<1>
+        |    x <= UInt(1)
+        |    y <= UInt<1>("h1")
+        |    top2wiring_y <= y
+        |  module B :
+        |    output x: UInt<1>
+        |    output topwiring_c1_x: UInt<1>
+        |    output topwiring_c2_x: UInt<1>
+        |    inst c1 of C
+        |    inst c2 of C
+        |    x <= UInt(1)
+        |    topwiring_c1_x <= c1.topwiring_x
+        |    topwiring_c2_x <= c2.topwiring_x
+        |  module C:
+        |    output x: UInt<1>
+        |    output topwiring_x: UInt<1>
+        |    x <= UInt(0)
+        |    topwiring_x <= x
            """.stripMargin
-      execute(input, check, topwiringannos)
-   }
+    execute(input, check, topwiringannos)
+  }
 
-   "The signal fullword in module C inst c1 and c2 and signal y in module A_" should
-   s"be connected to Top port with topwiring and top2wiring prefix and outfile in $testDirName" in {
-      val input =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |    inst a2 of A_
-           |  module A :
-           |    output fullword: UInt<1>
-           |    fullword <= UInt(1)
-           |    inst b1 of B
-           |  module A_ :
-           |    output fullword: UInt<1>
-           |    wire y : UInt<1>
-           |    y <= UInt(1)
-           |    fullword <= UInt(1)
-           |  module B :
-           |    output fullword: UInt<1>
-           |    fullword <= UInt(1)
-           |    inst c1 of C
-           |    inst c2 of C
-           |  module C:
-           |    output fullword: UInt<1>
-           |    fullword <= UInt(0)
+  "The signal fullword in module C inst c1 and c2 and signal y in module A_" should
+    s"be connected to Top port with topwiring and top2wiring prefix and outfile in $testDirName" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A :
+        |    output fullword: UInt<1>
+        |    fullword <= UInt(1)
+        |    inst b1 of B
+        |  module A_ :
+        |    output fullword: UInt<1>
+        |    wire y : UInt<1>
+        |    y <= UInt(1)
+        |    fullword <= UInt(1)
+        |  module B :
+        |    output fullword: UInt<1>
+        |    fullword <= UInt(1)
+        |    inst c1 of C
+        |    inst c2 of C
+        |  module C:
+        |    output fullword: UInt<1>
+        |    fullword <= UInt(0)
            """.stripMargin
-      val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"fullword",
-                                                                 ModuleName(s"C", CircuitName(s"Top"))),
-                                                   s"topwiring_"),
-                               TopWiringAnnotation(ComponentName(s"y",
-                                                                 ModuleName(s"A_", CircuitName(s"Top"))),
-                                                   s"top2wiring_"),
-                         TopWiringOutputFilesAnnotation(testDirName, topWiringTestOutputFilesFunction))
-      val check =
-         """circuit Top :
-           |  module Top :
-           |    output topwiring_a1_b1_c1_fullword: UInt<1>
-           |    output topwiring_a1_b1_c2_fullword: UInt<1>
-           |    output top2wiring_a2_y: UInt<1>
-           |    inst a1 of A
-           |    inst a2 of A_
-           |    topwiring_a1_b1_c1_fullword <= a1.topwiring_b1_c1_fullword
-           |    topwiring_a1_b1_c2_fullword <= a1.topwiring_b1_c2_fullword
-           |    top2wiring_a2_y <= a2.top2wiring_y
-           |  module A :
-           |    output fullword: UInt<1>
-           |    output topwiring_b1_c1_fullword: UInt<1>
-           |    output topwiring_b1_c2_fullword: UInt<1>
-           |    inst b1 of B
-           |    fullword <= UInt(1)
-           |    topwiring_b1_c1_fullword <= b1.topwiring_c1_fullword
-           |    topwiring_b1_c2_fullword <= b1.topwiring_c2_fullword
-           |  module A_ :
-           |    output fullword: UInt<1>
-           |    output top2wiring_y: UInt<1>
-           |    wire y : UInt<1>
-           |    fullword <= UInt(1)
-           |    y <= UInt<1>("h1")
-           |    top2wiring_y <= y
-           |  module B :
-           |    output fullword: UInt<1>
-           |    output topwiring_c1_fullword: UInt<1>
-           |    output topwiring_c2_fullword: UInt<1>
-           |    inst c1 of C
-           |    inst c2 of C
-           |    fullword <= UInt(1)
-           |    topwiring_c1_fullword <= c1.topwiring_fullword
-           |    topwiring_c2_fullword <= c2.topwiring_fullword
-           |  module C:
-           |    output fullword: UInt<1>
-           |    output topwiring_fullword: UInt<1>
-           |    fullword <= UInt(0)
-           |    topwiring_fullword <= fullword
+    val topwiringannos = Seq(
+      TopWiringAnnotation(ComponentName(s"fullword", ModuleName(s"C", CircuitName(s"Top"))), s"topwiring_"),
+      TopWiringAnnotation(ComponentName(s"y", ModuleName(s"A_", CircuitName(s"Top"))), s"top2wiring_"),
+      TopWiringOutputFilesAnnotation(testDirName, topWiringTestOutputFilesFunction)
+    )
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    output topwiring_a1_b1_c1_fullword: UInt<1>
+        |    output topwiring_a1_b1_c2_fullword: UInt<1>
+        |    output top2wiring_a2_y: UInt<1>
+        |    inst a1 of A
+        |    inst a2 of A_
+        |    topwiring_a1_b1_c1_fullword <= a1.topwiring_b1_c1_fullword
+        |    topwiring_a1_b1_c2_fullword <= a1.topwiring_b1_c2_fullword
+        |    top2wiring_a2_y <= a2.top2wiring_y
+        |  module A :
+        |    output fullword: UInt<1>
+        |    output topwiring_b1_c1_fullword: UInt<1>
+        |    output topwiring_b1_c2_fullword: UInt<1>
+        |    inst b1 of B
+        |    fullword <= UInt(1)
+        |    topwiring_b1_c1_fullword <= b1.topwiring_c1_fullword
+        |    topwiring_b1_c2_fullword <= b1.topwiring_c2_fullword
+        |  module A_ :
+        |    output fullword: UInt<1>
+        |    output top2wiring_y: UInt<1>
+        |    wire y : UInt<1>
+        |    fullword <= UInt(1)
+        |    y <= UInt<1>("h1")
+        |    top2wiring_y <= y
+        |  module B :
+        |    output fullword: UInt<1>
+        |    output topwiring_c1_fullword: UInt<1>
+        |    output topwiring_c2_fullword: UInt<1>
+        |    inst c1 of C
+        |    inst c2 of C
+        |    fullword <= UInt(1)
+        |    topwiring_c1_fullword <= c1.topwiring_fullword
+        |    topwiring_c2_fullword <= c2.topwiring_fullword
+        |  module C:
+        |    output fullword: UInt<1>
+        |    output topwiring_fullword: UInt<1>
+        |    fullword <= UInt(0)
+        |    topwiring_fullword <= fullword
            """.stripMargin
-      execute(input, check, topwiringannos)
-   }
-
+    execute(input, check, topwiringannos)
+  }
 
-   "The signal fullword in module C inst c1 and c2 and signal fullword in module B" should
-   s"be connected to Top port with topwiring prefix" in {
-      val input =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |    inst a2 of A_
-           |  module A :
-           |    output fullword: UInt<1>
-           |    fullword <= UInt(1)
-           |    inst b1 of B
-           |  module A_ :
-           |    output fullword: UInt<1>
-           |    wire y : UInt<1>
-           |    y <= UInt(1)
-           |    fullword <= UInt(1)
-           |  module B :
-           |    output fullword: UInt<1>
-           |    fullword <= UInt(1)
-           |    inst c1 of C
-           |    inst c2 of C
-           |  module C:
-           |    output fullword: UInt<1>
-           |    fullword <= UInt(0)
+  "The signal fullword in module C inst c1 and c2 and signal fullword in module B" should
+    s"be connected to Top port with topwiring prefix" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A :
+        |    output fullword: UInt<1>
+        |    fullword <= UInt(1)
+        |    inst b1 of B
+        |  module A_ :
+        |    output fullword: UInt<1>
+        |    wire y : UInt<1>
+        |    y <= UInt(1)
+        |    fullword <= UInt(1)
+        |  module B :
+        |    output fullword: UInt<1>
+        |    fullword <= UInt(1)
+        |    inst c1 of C
+        |    inst c2 of C
+        |  module C:
+        |    output fullword: UInt<1>
+        |    fullword <= UInt(0)
            """.stripMargin
-     val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"fullword",
-                                                                 ModuleName(s"C", CircuitName(s"Top"))),
-                                                   s"topwiring_"),
-                               TopWiringAnnotation(ComponentName(s"fullword",
-                                                                 ModuleName(s"B", CircuitName(s"Top"))),
-                                                   s"topwiring_"))
-     val check =
-         """circuit Top :
-           |  module Top :
-           |    output topwiring_a1_b1_fullword: UInt<1>
-           |    output topwiring_a1_b1_c1_fullword: UInt<1>
-           |    output topwiring_a1_b1_c2_fullword: UInt<1>
-           |    inst a1 of A
-           |    inst a2 of A_
-           |    topwiring_a1_b1_fullword <= a1.topwiring_b1_fullword
-           |    topwiring_a1_b1_c1_fullword <= a1.topwiring_b1_c1_fullword
-           |    topwiring_a1_b1_c2_fullword <= a1.topwiring_b1_c2_fullword
-           |  module A :
-           |    output fullword: UInt<1>
-           |    output topwiring_b1_fullword: UInt<1>
-           |    output topwiring_b1_c1_fullword: UInt<1>
-           |    output topwiring_b1_c2_fullword: UInt<1>
-           |    inst b1 of B
-           |    fullword <= UInt(1)
-           |    topwiring_b1_fullword <= b1.topwiring_fullword
-           |    topwiring_b1_c1_fullword <= b1.topwiring_c1_fullword
-           |    topwiring_b1_c2_fullword <= b1.topwiring_c2_fullword
-           |  module A_ :
-           |    output fullword: UInt<1>
-           |    wire y : UInt<1>
-           |    fullword <= UInt(1)
-           |    y <= UInt<1>("h1")
-           |  module B :
-           |    output fullword: UInt<1>
-           |    output topwiring_fullword: UInt<1>
-           |    output topwiring_c1_fullword: UInt<1>
-           |    output topwiring_c2_fullword: UInt<1>
-           |    inst c1 of C
-           |    inst c2 of C
-           |    fullword <= UInt(1)
-           |    topwiring_fullword <= fullword
-           |    topwiring_c1_fullword <= c1.topwiring_fullword
-           |    topwiring_c2_fullword <= c2.topwiring_fullword
-           |  module C:
-           |    output fullword: UInt<1>
-           |    output topwiring_fullword: UInt<1>
-           |    fullword <= UInt(0)
-           |    topwiring_fullword <= fullword
+    val topwiringannos = Seq(
+      TopWiringAnnotation(ComponentName(s"fullword", ModuleName(s"C", CircuitName(s"Top"))), s"topwiring_"),
+      TopWiringAnnotation(ComponentName(s"fullword", ModuleName(s"B", CircuitName(s"Top"))), s"topwiring_")
+    )
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    output topwiring_a1_b1_fullword: UInt<1>
+        |    output topwiring_a1_b1_c1_fullword: UInt<1>
+        |    output topwiring_a1_b1_c2_fullword: UInt<1>
+        |    inst a1 of A
+        |    inst a2 of A_
+        |    topwiring_a1_b1_fullword <= a1.topwiring_b1_fullword
+        |    topwiring_a1_b1_c1_fullword <= a1.topwiring_b1_c1_fullword
+        |    topwiring_a1_b1_c2_fullword <= a1.topwiring_b1_c2_fullword
+        |  module A :
+        |    output fullword: UInt<1>
+        |    output topwiring_b1_fullword: UInt<1>
+        |    output topwiring_b1_c1_fullword: UInt<1>
+        |    output topwiring_b1_c2_fullword: UInt<1>
+        |    inst b1 of B
+        |    fullword <= UInt(1)
+        |    topwiring_b1_fullword <= b1.topwiring_fullword
+        |    topwiring_b1_c1_fullword <= b1.topwiring_c1_fullword
+        |    topwiring_b1_c2_fullword <= b1.topwiring_c2_fullword
+        |  module A_ :
+        |    output fullword: UInt<1>
+        |    wire y : UInt<1>
+        |    fullword <= UInt(1)
+        |    y <= UInt<1>("h1")
+        |  module B :
+        |    output fullword: UInt<1>
+        |    output topwiring_fullword: UInt<1>
+        |    output topwiring_c1_fullword: UInt<1>
+        |    output topwiring_c2_fullword: UInt<1>
+        |    inst c1 of C
+        |    inst c2 of C
+        |    fullword <= UInt(1)
+        |    topwiring_fullword <= fullword
+        |    topwiring_c1_fullword <= c1.topwiring_fullword
+        |    topwiring_c2_fullword <= c2.topwiring_fullword
+        |  module C:
+        |    output fullword: UInt<1>
+        |    output topwiring_fullword: UInt<1>
+        |    fullword <= UInt(0)
+        |    topwiring_fullword <= fullword
            """.stripMargin
-      execute(input, check, topwiringannos)
-   }
+    execute(input, check, topwiringannos)
+  }
 
-   "TopWiringTransform" should "do nothing if run without TopWiring* annotations" in {
-     val input = """|circuit Top :
-                    |  module Top :
-                    |    input foo : UInt<1>""".stripMargin
-     val inputFile = {
-       val fileName = s"${testDir.getAbsolutePath}/input-no-sources.fir"
-       val w = new PrintWriter(fileName)
-       w.write(input)
-       w.close()
-       fileName
-     }
-     val args = Array(
-       "--custom-transforms", "firrtl.transforms.TopWiring.TopWiringTransform",
-       "--input-file", inputFile,
-       "--top-name", "Top",
-       "--compiler", "low",
-       "--info-mode", "ignore"
-     )
-     firrtl.Driver.execute(args) match {
-       case FirrtlExecutionSuccess(_, emitted) =>
-         parse(emitted).serialize should be (parse(input).serialize)
-       case _ => fail
-     }
-   }
+  "TopWiringTransform" should "do nothing if run without TopWiring* annotations" in {
+    val input = """|circuit Top :
+                   |  module Top :
+                   |    input foo : UInt<1>""".stripMargin
+    val inputFile = {
+      val fileName = s"${testDir.getAbsolutePath}/input-no-sources.fir"
+      val w = new PrintWriter(fileName)
+      w.write(input)
+      w.close()
+      fileName
+    }
+    val args = Array(
+      "--custom-transforms",
+      "firrtl.transforms.TopWiring.TopWiringTransform",
+      "--input-file",
+      inputFile,
+      "--top-name",
+      "Top",
+      "--compiler",
+      "low",
+      "--info-mode",
+      "ignore"
+    )
+    firrtl.Driver.execute(args) match {
+      case FirrtlExecutionSuccess(_, emitted) =>
+        parse(emitted).serialize should be(parse(input).serialize)
+      case _ => fail
+    }
+  }
 
-   "TopWiringTransform" should "remove TopWiringAnnotations" in {
-     val input =
-       """|circuit Top:
-          |  module Top:
-          |    wire foo: UInt<1>""".stripMargin
+  "TopWiringTransform" should "remove TopWiringAnnotations" in {
+    val input =
+      """|circuit Top:
+         |  module Top:
+         |    wire foo: UInt<1>""".stripMargin
 
-     val bar =
-       Target
-         .deserialize("~Top|Top>foo")
-         .toNamed match { case a: ComponentName => a }
+    val bar =
+      Target
+        .deserialize("~Top|Top>foo")
+        .toNamed match { case a: ComponentName => a }
 
-     val annotations = Seq(TopWiringAnnotation(bar, "bar_"))
-     val outputState = (new TopWiringTransform).execute(CircuitState(Parser.parse(input), MidForm, annotations, None))
+    val annotations = Seq(TopWiringAnnotation(bar, "bar_"))
+    val outputState = (new TopWiringTransform).execute(CircuitState(Parser.parse(input), MidForm, annotations, None))
 
-     outputState.circuit.serialize should include ("output bar_foo")
-     outputState.annotations.toSeq should be (empty)
-   }
+    outputState.circuit.serialize should include("output bar_foo")
+    outputState.annotations.toSeq should be(empty)
+  }
 }
 
 class AggregateTopWiringTests extends MiddleTransformSpec with TopWiringTestsCommon {
 
-   "An aggregate wire named myAgg in A" should s"be wired to Top's IO as topwiring_a1_myAgg" in {
-      val input =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |  module A:
-           |    wire myAgg: { a: UInt<1>, b: SInt<8> }
-           |    myAgg.a <= UInt(0)
-           |    myAgg.b <= SInt(-1)
+  "An aggregate wire named myAgg in A" should s"be wired to Top's IO as topwiring_a1_myAgg" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |  module A:
+        |    wire myAgg: { a: UInt<1>, b: SInt<8> }
+        |    myAgg.a <= UInt(0)
+        |    myAgg.b <= SInt(-1)
            """.stripMargin
-     val topwiringannos = Seq(TopWiringAnnotation(ComponentName(s"myAgg", ModuleName(s"A", CircuitName(s"Top"))),
-                                                   s"topwiring_"))
-     val check =
-         """circuit Top :
-           |  module Top :
-           |    output topwiring_a1_myAgg: { a: UInt<1>, b: SInt<8> }
-           |    inst a1 of A
-           |    topwiring_a1_myAgg.a <= a1.topwiring_myAgg.a
-           |    topwiring_a1_myAgg.b <= a1.topwiring_myAgg.b
-           |  module A :
-           |    output topwiring_myAgg: { a: UInt<1>, b: SInt<8> }
-           |    wire myAgg: { a: UInt<1>, b: SInt<8> }
-           |    myAgg.a <= UInt(0)
-           |    myAgg.b <= SInt(-1)
-           |    topwiring_myAgg.a <= myAgg.a
-           |    topwiring_myAgg.b <= myAgg.b
+    val topwiringannos =
+      Seq(TopWiringAnnotation(ComponentName(s"myAgg", ModuleName(s"A", CircuitName(s"Top"))), s"topwiring_"))
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    output topwiring_a1_myAgg: { a: UInt<1>, b: SInt<8> }
+        |    inst a1 of A
+        |    topwiring_a1_myAgg.a <= a1.topwiring_myAgg.a
+        |    topwiring_a1_myAgg.b <= a1.topwiring_myAgg.b
+        |  module A :
+        |    output topwiring_myAgg: { a: UInt<1>, b: SInt<8> }
+        |    wire myAgg: { a: UInt<1>, b: SInt<8> }
+        |    myAgg.a <= UInt(0)
+        |    myAgg.b <= SInt(-1)
+        |    topwiring_myAgg.a <= myAgg.a
+        |    topwiring_myAgg.b <= myAgg.b
            """.stripMargin
-      execute(input, check, topwiringannos)
-   }
+    execute(input, check, topwiringannos)
+  }
 
-   "Aggregate wires myAgg in Top.a1, Top.b.a1 and Top.b.a2" should
-   s"be wired to Top's IO as topwiring_a1_myAgg, topwiring_b_a1_myAgg, and topwiring_b_a2_myAgg" in {
-      val input =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |    inst b of B
-           |  module B:
-           |    inst a1 of A
-           |    inst a2 of A
-           |  module A:
-           |    wire myAgg: { a: UInt<1>, b: SInt<8> }
-           |    myAgg.a <= UInt(0)
-           |    myAgg.b <= SInt(-1)
+  "Aggregate wires myAgg in Top.a1, Top.b.a1 and Top.b.a2" should
+    s"be wired to Top's IO as topwiring_a1_myAgg, topwiring_b_a1_myAgg, and topwiring_b_a2_myAgg" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst b of B
+        |  module B:
+        |    inst a1 of A
+        |    inst a2 of A
+        |  module A:
+        |    wire myAgg: { a: UInt<1>, b: SInt<8> }
+        |    myAgg.a <= UInt(0)
+        |    myAgg.b <= SInt(-1)
            """.stripMargin
-     val topwiringannos = Seq(
-        TopWiringAnnotation(ComponentName(s"myAgg", ModuleName(s"A", CircuitName(s"Top"))), s"topwiring_"))
+    val topwiringannos =
+      Seq(TopWiringAnnotation(ComponentName(s"myAgg", ModuleName(s"A", CircuitName(s"Top"))), s"topwiring_"))
 
-     val check =
-         """circuit Top :
-           |  module Top :
-           |    output topwiring_a1_myAgg: { a: UInt<1>, b: SInt<8> }
-           |    output topwiring_b_a1_myAgg: { a: UInt<1>, b: SInt<8> }
-           |    output topwiring_b_a2_myAgg: { a: UInt<1>, b: SInt<8> }
-           |    inst a1 of A
-           |    inst b of B
-           |    topwiring_a1_myAgg.a <= a1.topwiring_myAgg.a
-           |    topwiring_a1_myAgg.b <= a1.topwiring_myAgg.b
-           |    topwiring_b_a1_myAgg.a <= b.topwiring_a1_myAgg.a
-           |    topwiring_b_a1_myAgg.b <= b.topwiring_a1_myAgg.b
-           |    topwiring_b_a2_myAgg.a <= b.topwiring_a2_myAgg.a
-           |    topwiring_b_a2_myAgg.b <= b.topwiring_a2_myAgg.b
-           |  module B:
-           |    output topwiring_a1_myAgg: { a: UInt<1>, b: SInt<8> }
-           |    output topwiring_a2_myAgg: { a: UInt<1>, b: SInt<8> }
-           |    inst a1 of A
-           |    inst a2 of A
-           |    topwiring_a1_myAgg.a <= a1.topwiring_myAgg.a
-           |    topwiring_a1_myAgg.b <= a1.topwiring_myAgg.b
-           |    topwiring_a2_myAgg.a <= a2.topwiring_myAgg.a
-           |    topwiring_a2_myAgg.b <= a2.topwiring_myAgg.b
-           |  module A :
-           |    output topwiring_myAgg: { a: UInt<1>, b: SInt<8> }
-           |    wire myAgg: { a: UInt<1>, b: SInt<8> }
-           |    myAgg.a <= UInt(0)
-           |    myAgg.b <= SInt(-1)
-           |    topwiring_myAgg.a <= myAgg.a
-           |    topwiring_myAgg.b <= myAgg.b
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    output topwiring_a1_myAgg: { a: UInt<1>, b: SInt<8> }
+        |    output topwiring_b_a1_myAgg: { a: UInt<1>, b: SInt<8> }
+        |    output topwiring_b_a2_myAgg: { a: UInt<1>, b: SInt<8> }
+        |    inst a1 of A
+        |    inst b of B
+        |    topwiring_a1_myAgg.a <= a1.topwiring_myAgg.a
+        |    topwiring_a1_myAgg.b <= a1.topwiring_myAgg.b
+        |    topwiring_b_a1_myAgg.a <= b.topwiring_a1_myAgg.a
+        |    topwiring_b_a1_myAgg.b <= b.topwiring_a1_myAgg.b
+        |    topwiring_b_a2_myAgg.a <= b.topwiring_a2_myAgg.a
+        |    topwiring_b_a2_myAgg.b <= b.topwiring_a2_myAgg.b
+        |  module B:
+        |    output topwiring_a1_myAgg: { a: UInt<1>, b: SInt<8> }
+        |    output topwiring_a2_myAgg: { a: UInt<1>, b: SInt<8> }
+        |    inst a1 of A
+        |    inst a2 of A
+        |    topwiring_a1_myAgg.a <= a1.topwiring_myAgg.a
+        |    topwiring_a1_myAgg.b <= a1.topwiring_myAgg.b
+        |    topwiring_a2_myAgg.a <= a2.topwiring_myAgg.a
+        |    topwiring_a2_myAgg.b <= a2.topwiring_myAgg.b
+        |  module A :
+        |    output topwiring_myAgg: { a: UInt<1>, b: SInt<8> }
+        |    wire myAgg: { a: UInt<1>, b: SInt<8> }
+        |    myAgg.a <= UInt(0)
+        |    myAgg.b <= SInt(-1)
+        |    topwiring_myAgg.a <= myAgg.a
+        |    topwiring_myAgg.b <= myAgg.b
            """.stripMargin
-      execute(input, check, topwiringannos)
-   }
+    execute(input, check, topwiringannos)
+  }
 }