diff options
| author | Jiuyang Liu | 2021-11-30 11:16:02 +0800 |
|---|---|---|
| committer | GitHub | 2021-11-30 03:16:02 +0000 |
| commit | a4d13a5024f7488e1d2b9fdd27d3917157a67268 (patch) | |
| tree | 7e39f9ba6957825c6e4682abdfc93a16f54cc898 /src/test/scala/firrtlTests/execution/VerilogExecution.scala | |
| parent | c43879f8fc34eff92965896923fc8780efc07a03 (diff) | |
[deprecation clean up] remove trait firrtl.util.BackendCompilationUtilities (#2423)
Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'src/test/scala/firrtlTests/execution/VerilogExecution.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/execution/VerilogExecution.scala | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/execution/VerilogExecution.scala b/src/test/scala/firrtlTests/execution/VerilogExecution.scala index fe6e1832..01da57a0 100644 --- a/src/test/scala/firrtlTests/execution/VerilogExecution.scala +++ b/src/test/scala/firrtlTests/execution/VerilogExecution.scala @@ -3,12 +3,11 @@ package firrtlTests.execution import java.io.File - import firrtl._ import firrtl.ir._ - import firrtl.stage.{FirrtlCircuitAnnotation, FirrtlStage} import firrtl.options.TargetDirAnnotation +import firrtl.util.BackendCompilationUtilities._ /** * Mixing in this trait causes a SimpleExecutionTest to be run in Verilog simulation. |