diff options
| author | Jack Koenig | 2019-11-29 16:59:34 -0800 |
|---|---|---|
| committer | Jack Koenig | 2020-01-07 19:35:50 -0800 |
| commit | 3e75cba35630c9831cf7833c4947df1dfed93eb6 (patch) | |
| tree | a4179bfe56af672ec0f1ab9c8868f9825387710b /src/test/scala/firrtlTests/annotationTests | |
| parent | 0bc0bcd598ccb8f0251a93d546270fcfdfa47fdd (diff) | |
Remove printlns from tests
Diffstat (limited to 'src/test/scala/firrtlTests/annotationTests')
| -rw-r--r-- | src/test/scala/firrtlTests/annotationTests/TargetSpec.scala | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala index da154b6a..1bc4c927 100644 --- a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala +++ b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala @@ -9,7 +9,6 @@ import firrtlTests.FirrtlPropSpec class TargetSpec extends FirrtlPropSpec { def check(comp: Target): Unit = { val named = Target.convertTarget2Named(comp) - println(named) val comp2 = Target.convertNamed2Target(named) assert(comp.toGenericTarget.complete == comp2) } @@ -43,7 +42,6 @@ class TargetSpec extends FirrtlPropSpec { val x_reg0_data = top.instOf("x", "X").ref("reg0").field("data") top.instOf("x", "x") top.ref("y") - println(x_reg0_data) } property("Should serialize and deserialize") { val circuit = CircuitTarget("Circuit") |