All of src/ formatted with scalafmt

1 files changed, 65 insertions, 54 deletions

diff --git a/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala b/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala
index a0d444b3..e134f6e5 100644
--- a/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala
+++ b/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala
@@ -9,10 +9,10 @@ import firrtl.testutils._
 
 class InstanceGraphTests extends FirrtlFlatSpec {
   private def getEdgeSet(graph: DiGraph[String]): collection.Map[String, collection.Set[String]] = {
-    (graph.getVertices map {v => (v, graph.getEdges(v))}).toMap
+    (graph.getVertices.map { v => (v, graph.getEdges(v)) }).toMap
   }
 
-  behavior of "InstanceGraph"
+  behavior.of("InstanceGraph")
 
   it should "recognize a simple hierarchy" in {
     val input = """
@@ -33,7 +33,13 @@ circuit Top :
 """
     val circuit = ToWorkingIR.run(parse(input))
     val graph = new InstanceGraph(circuit).graph.transformNodes(_.module)
-    getEdgeSet(graph) shouldBe Map("Top" -> Set("Child1", "Child2"), "Child1" -> Set("Child1a", "Child1b"), "Child2" -> Set(), "Child1a" -> Set(), "Child1b" -> Set())
+    getEdgeSet(graph) shouldBe Map(
+      "Top" -> Set("Child1", "Child2"),
+      "Child1" -> Set("Child1a", "Child1b"),
+      "Child2" -> Set(),
+      "Child1a" -> Set(),
+      "Child1b" -> Set()
+    )
   }
 
   it should "find hierarchical instances correctly in disconnected hierarchies" in {
@@ -97,12 +103,20 @@ circuit Top :
 """
     val circuit = ToWorkingIR.run(parse(input))
     val graph = new InstanceGraph(circuit).graph.transformNodes(_.module)
-    getEdgeSet(graph) shouldBe Map("Top" -> Set("Child1"), "Top2" -> Set("Child2", "Child3"), "Child2" -> Set("Child2a", "Child2b"), "Child1" -> Set(), "Child2a" -> Set(), "Child2b" -> Set(), "Child3" -> Set())
+    getEdgeSet(graph) shouldBe Map(
+      "Top" -> Set("Child1"),
+      "Top2" -> Set("Child2", "Child3"),
+      "Child2" -> Set("Child2a", "Child2b"),
+      "Child1" -> Set(),
+      "Child2a" -> Set(),
+      "Child2b" -> Set(),
+      "Child3" -> Set()
+    )
   }
 
   it should "not drop duplicate nodes when they collide as a result of transformNodes" in {
     val input =
-"""circuit Top :
+      """circuit Top :
   module Buzz :
     skip
   module Fizz :
@@ -134,70 +148,70 @@ circuit Top :
   // experience non-determinism
   it should "preserve Module declaration order" in {
     val input = """
-      |circuit Top :
-      |  module Top :
-      |    inst c1 of Child1
-      |    inst c2 of Child2
-      |  module Child1 :
-      |    inst a of Child1a
-      |    inst b of Child1b
-      |    skip
-      |  module Child1a :
-      |    skip
-      |  module Child1b :
-      |    skip
-      |  module Child2 :
-      |    skip
-      |""".stripMargin
+                  |circuit Top :
+                  |  module Top :
+                  |    inst c1 of Child1
+                  |    inst c2 of Child2
+                  |  module Child1 :
+                  |    inst a of Child1a
+                  |    inst b of Child1b
+                  |    skip
+                  |  module Child1a :
+                  |    skip
+                  |  module Child1b :
+                  |    skip
+                  |  module Child2 :
+                  |    skip
+                  |""".stripMargin
     val circuit = ToWorkingIR.run(parse(input))
     val instGraph = new InstanceGraph(circuit)
     val childMap = instGraph.getChildrenInstances
-    childMap.keys.toSeq should equal (Seq("Top", "Child1", "Child1a", "Child1b", "Child2"))
+    childMap.keys.toSeq should equal(Seq("Top", "Child1", "Child1a", "Child1b", "Child2"))
   }
 
   // Note that due to optimized implementations of Map1-4, at least 5 entries are needed to
   // experience non-determinism
   it should "preserve Instance declaration order" in {
     val input = """
-      |circuit Top :
-      |  module Top :
-      |    inst a of Child
-      |    inst b of Child
-      |    inst c of Child
-      |    inst d of Child
-      |    inst e of Child
-      |    inst f of Child
-      |  module Child :
-      |    skip
-      |""".stripMargin
+                  |circuit Top :
+                  |  module Top :
+                  |    inst a of Child
+                  |    inst b of Child
+                  |    inst c of Child
+                  |    inst d of Child
+                  |    inst e of Child
+                  |    inst f of Child
+                  |  module Child :
+                  |    skip
+                  |""".stripMargin
     val circuit = ToWorkingIR.run(parse(input))
     val instGraph = new InstanceGraph(circuit)
     val childMap = instGraph.getChildrenInstances
     val insts = childMap("Top").toSeq.map(_.name)
-    insts should equal (Seq("a", "b", "c", "d", "e", "f"))
+    insts should equal(Seq("a", "b", "c", "d", "e", "f"))
   }
 
   // Note that due to optimized implementations of Map1-4, at least 5 entries are needed to
   // experience non-determinism
   it should "have defined fullHierarchy order" in {
     val input = """
-      |circuit Top :
-      |  module Top :
-      |    inst a of Child
-      |    inst b of Child
-      |    inst c of Child
-      |    inst d of Child
-      |    inst e of Child
-      |  module Child :
-      |    skip
-      |""".stripMargin
+                  |circuit Top :
+                  |  module Top :
+                  |    inst a of Child
+                  |    inst b of Child
+                  |    inst c of Child
+                  |    inst d of Child
+                  |    inst e of Child
+                  |  module Child :
+                  |    skip
+                  |""".stripMargin
     val circuit = ToWorkingIR.run(parse(input))
     val instGraph = new InstanceGraph(circuit)
     val hier = instGraph.fullHierarchy
-    hier.keys.toSeq.map(_.name) should equal (Seq("Top", "a", "b", "c", "d", "e"))
+    hier.keys.toSeq.map(_.name) should equal(Seq("Top", "a", "b", "c", "d", "e"))
   }
 
-  behavior of "InstanceGraph.staticInstanceCount"
+  behavior.of("InstanceGraph.staticInstanceCount")
 
   it should "report that there is one instance of the top module" in {
     val input =
@@ -207,7 +221,7 @@ circuit Top :
          |""".stripMargin
     val iGraph = new InstanceGraph(ToWorkingIR.run(parse(input)))
     val expectedCounts = Map(OfModule("Foo") -> 1)
-    iGraph.staticInstanceCount should be (expectedCounts)
+    iGraph.staticInstanceCount should be(expectedCounts)
   }
 
   it should "report correct number of instances for a sample circuit" in {
@@ -225,10 +239,8 @@ circuit Top :
          |    inst bar2 of Bar
          |""".stripMargin
     val iGraph = new InstanceGraph(ToWorkingIR.run(parse(input)))
-    val expectedCounts = Map(OfModule("Foo") -> 1,
-                             OfModule("Bar") -> 2,
-                             OfModule("Baz") -> 3)
-    iGraph.staticInstanceCount should be (expectedCounts)
+    val expectedCounts = Map(OfModule("Foo") -> 1, OfModule("Bar") -> 2, OfModule("Baz") -> 3)
+    iGraph.staticInstanceCount should be(expectedCounts)
   }
 
   it should "report zero instances for dead modules" in {
@@ -240,12 +252,11 @@ circuit Top :
          |    skip
          |""".stripMargin
     val iGraph = new InstanceGraph(ToWorkingIR.run(parse(input)))
-    val expectedCounts = Map(OfModule("Foo") -> 1,
-                             OfModule("Bar") -> 0)
-    iGraph.staticInstanceCount should be (expectedCounts)
+    val expectedCounts = Map(OfModule("Foo") -> 1, OfModule("Bar") -> 0)
+    iGraph.staticInstanceCount should be(expectedCounts)
   }
 
-  behavior of "Reachable/Unreachable helper methods"
+  behavior.of("Reachable/Unreachable helper methods")
 
   they should "report correct reachable/unreachable counts" in {
     val input =