All of src/ formatted with scalafmt

5 files changed, 190 insertions, 153 deletions

diff --git a/src/test/scala/firrtlTests/analyses/CircuitGraphSpec.scala b/src/test/scala/firrtlTests/analyses/CircuitGraphSpec.scala
index 79922fa9..0f0d5d47 100644
--- a/src/test/scala/firrtlTests/analyses/CircuitGraphSpec.scala
+++ b/src/test/scala/firrtlTests/analyses/CircuitGraphSpec.scala
@@ -11,40 +11,42 @@ import firrtl.testutils.FirrtlFlatSpec
 import firrtl.{ChirrtlForm, CircuitState, FileUtils, UnknownForm}
 
 class CircuitGraphSpec extends FirrtlFlatSpec {
-    "CircuitGraph" should "find paths with deep hierarchy quickly" in {
-      def mkChild(n: Int): String =
-        s"""  module Child${n} :
-           |    input in: UInt<8>
-           |    output out: UInt<8>
-           |    inst c1 of Child${n+1}
-           |    inst c2 of Child${n+1}
-           |    c1.in <= in
-           |    c2.in <= c1.out
-           |    out <= c2.out
+  "CircuitGraph" should "find paths with deep hierarchy quickly" in {
+    def mkChild(n: Int): String =
+      s"""  module Child${n} :
+         |    input in: UInt<8>
+         |    output out: UInt<8>
+         |    inst c1 of Child${n + 1}
+         |    inst c2 of Child${n + 1}
+         |    c1.in <= in
+         |    c2.in <= c1.out
+         |    out <= c2.out
          """.stripMargin
-      def mkLeaf(n: Int): String =
-        s"""  module Child${n} :
-           |    input in: UInt<8>
-           |    output out: UInt<8>
-           |    wire middle: UInt<8>
-           |    middle <= in
-           |    out <= middle
+    def mkLeaf(n: Int): String =
+      s"""  module Child${n} :
+         |    input in: UInt<8>
+         |    output out: UInt<8>
+         |    wire middle: UInt<8>
+         |    middle <= in
+         |    out <= middle
          """.stripMargin
-      (2 until 23 by 2).foreach { n =>
-        val input = new StringBuilder()
-        input ++=
-          """circuit Child0:
-            |""".stripMargin
-        (0 until n).foreach { i => input ++= mkChild(i); input ++= "\n" }
-        input ++= mkLeaf(n)
-        val circuit = new firrtl.stage.transforms.Compiler(Seq(Dependency[ExpandWhensAndCheck])).runTransform(
+    (2 until 23 by 2).foreach { n =>
+      val input = new StringBuilder()
+      input ++=
+        """circuit Child0:
+          |""".stripMargin
+      (0 until n).foreach { i => input ++= mkChild(i); input ++= "\n" }
+      input ++= mkLeaf(n)
+      val circuit = new firrtl.stage.transforms.Compiler(Seq(Dependency[ExpandWhensAndCheck]))
+        .runTransform(
           CircuitState(parse(input.toString()), UnknownForm)
-        ).circuit
-        val circuitGraph = CircuitGraph(circuit)
-        val C = CircuitTarget("Child0")
-        val Child0 = C.module("Child0")
-        circuitGraph.connectionPath(Child0.ref("in"), Child0.ref("out"))
-      }
+        )
+        .circuit
+      val circuitGraph = CircuitGraph(circuit)
+      val C = CircuitTarget("Child0")
+      val Child0 = C.module("Child0")
+      circuitGraph.connectionPath(Child0.ref("in"), Child0.ref("out"))
     }
+  }
 
 }
diff --git a/src/test/scala/firrtlTests/analyses/ConnectionGraphSpec.scala b/src/test/scala/firrtlTests/analyses/ConnectionGraphSpec.scala
index 06f59a3c..e08b7efc 100644
--- a/src/test/scala/firrtlTests/analyses/ConnectionGraphSpec.scala
+++ b/src/test/scala/firrtlTests/analyses/ConnectionGraphSpec.scala
@@ -14,9 +14,11 @@ class ConnectionGraphSpec extends FirrtlFlatSpec {
 
   "ConnectionGraph" should "build connection graph for rocket-chip" in {
     ConnectionGraph(
-      new firrtl.stage.transforms.Compiler(Seq(Dependency[ExpandWhensAndCheck])).runTransform(
-        CircuitState(parse(FileUtils.getTextResource("/regress/RocketCore.fir")), UnknownForm)
-      ).circuit
+      new firrtl.stage.transforms.Compiler(Seq(Dependency[ExpandWhensAndCheck]))
+        .runTransform(
+          CircuitState(parse(FileUtils.getTextResource("/regress/RocketCore.fir")), UnknownForm)
+        )
+        .circuit
     )
   }
 
@@ -44,9 +46,11 @@ class ConnectionGraphSpec extends FirrtlFlatSpec {
       |    out <= in
       |""".stripMargin
 
-  val circuit = new firrtl.stage.transforms.Compiler(Seq(Dependency[ExpandWhensAndCheck])).runTransform(
-    CircuitState(parse(input), UnknownForm)
-  ).circuit
+  val circuit = new firrtl.stage.transforms.Compiler(Seq(Dependency[ExpandWhensAndCheck]))
+    .runTransform(
+      CircuitState(parse(input), UnknownForm)
+    )
+    .circuit
 
   "ConnectionGraph" should "work with pathsInDAG" in {
     val Test = ModuleTarget("Test", "Test")
diff --git a/src/test/scala/firrtlTests/analyses/IRLookupSpec.scala b/src/test/scala/firrtlTests/analyses/IRLookupSpec.scala
index 50ee75ac..b1e9fd73 100644
--- a/src/test/scala/firrtlTests/analyses/IRLookupSpec.scala
+++ b/src/test/scala/firrtlTests/analyses/IRLookupSpec.scala
@@ -10,7 +10,6 @@ import firrtl.passes.ExpandWhensAndCheck
 import firrtl.stage.{Forms, TransformManager}
 import firrtl.testutils.FirrtlFlatSpec
 
-
 class IRLookupSpec extends FirrtlFlatSpec {
 
   "IRLookup" should "return declarations" in {
@@ -38,9 +37,11 @@ class IRLookupSpec extends FirrtlFlatSpec {
         |    out <= UInt(1)
         |""".stripMargin
 
-    val circuit = new firrtl.stage.transforms.Compiler(Seq(Dependency[ExpandWhensAndCheck])).runTransform(
-      CircuitState(parse(input), UnknownForm)
-    ).circuit
+    val circuit = new firrtl.stage.transforms.Compiler(Seq(Dependency[ExpandWhensAndCheck]))
+      .runTransform(
+        CircuitState(parse(input), UnknownForm)
+      )
+      .circuit
     val irLookup = IRLookup(circuit)
     val Test = ModuleTarget("Test", "Test")
     val uint8 = UIntType(IntWidth(8))
@@ -49,7 +50,10 @@ class IRLookupSpec extends FirrtlFlatSpec {
     irLookup.declaration(Test.ref("clk")) shouldBe Port(NoInfo, "clk", Input, ClockType)
     irLookup.declaration(Test.ref("reset")) shouldBe Port(NoInfo, "reset", Input, UIntType(IntWidth(1)))
 
-    val out = Port(NoInfo, "out", Output,
+    val out = Port(
+      NoInfo,
+      "out",
+      Output,
       BundleType(Seq(Field("a", Default, uint8), Field("b", Default, VectorType(uint8, 2))))
     )
     irLookup.declaration(Test.ref("out")) shouldBe out
@@ -73,7 +77,8 @@ class IRLookupSpec extends FirrtlFlatSpec {
     irLookup.declaration(Test.ref("y")) shouldBe DefWire(NoInfo, "y", uint8)
 
     irLookup.declaration(Test.ref("@and#0")) shouldBe
-      DoPrim(PrimOps.And,
+      DoPrim(
+        PrimOps.And,
         Seq(WRef("y", uint8, WireKind, SourceFlow), DoPrim(AsUInt, Seq(SIntLiteral(-1)), Nil, UIntType(IntWidth(1)))),
         Nil,
         uint8
@@ -84,12 +89,14 @@ class IRLookupSpec extends FirrtlFlatSpec {
     irLookup.declaration(Test.ref("child").field("out")) shouldBe inst
     irLookup.declaration(Test.instOf("child", "Child").ref("out")) shouldBe Port(NoInfo, "out", Output, uint8)
 
-    intercept[IllegalArgumentException]{ irLookup.declaration(Test.instOf("child", "Child").ref("missing")) }
-    intercept[IllegalArgumentException]{ irLookup.declaration(Test.instOf("child", "Missing").ref("out")) }
-    intercept[IllegalArgumentException]{ irLookup.declaration(Test.instOf("missing", "Child").ref("out")) }
-    intercept[IllegalArgumentException]{ irLookup.declaration(Test.ref("missing")) }
-    intercept[IllegalArgumentException]{ irLookup.declaration(Test.ref("out").field("c")) }
-    intercept[IllegalArgumentException]{ irLookup.declaration(Test.instOf("child", "Child").ref("out").field("missing")) }
+    intercept[IllegalArgumentException] { irLookup.declaration(Test.instOf("child", "Child").ref("missing")) }
+    intercept[IllegalArgumentException] { irLookup.declaration(Test.instOf("child", "Missing").ref("out")) }
+    intercept[IllegalArgumentException] { irLookup.declaration(Test.instOf("missing", "Child").ref("out")) }
+    intercept[IllegalArgumentException] { irLookup.declaration(Test.ref("missing")) }
+    intercept[IllegalArgumentException] { irLookup.declaration(Test.ref("out").field("c")) }
+    intercept[IllegalArgumentException] {
+      irLookup.declaration(Test.instOf("child", "Child").ref("out").field("missing"))
+    }
   }
 
   "IRLookup" should "return mem declarations" in {
@@ -152,9 +159,11 @@ class IRLookupSpec extends FirrtlFlatSpec {
     val Readwriter = Mem.field("rw")
     val allSignals = readerTargets(Reader) ++ writerTargets(Writer) ++ readwriterTargets(Readwriter)
 
-    val circuit = new firrtl.stage.transforms.Compiler(Seq(Dependency[ExpandWhensAndCheck])).runTransform(
-      CircuitState(parse(input), UnknownForm)
-    ).circuit
+    val circuit = new firrtl.stage.transforms.Compiler(Seq(Dependency[ExpandWhensAndCheck]))
+      .runTransform(
+        CircuitState(parse(input), UnknownForm)
+      )
+      .circuit
     val irLookup = IRLookup(circuit)
     val uint8 = UIntType(IntWidth(8))
     val mem = DefMemory(NoInfo, "m", uint8, 2, 1, 0, Seq("r"), Seq("w"), Seq("rw"))
@@ -188,9 +197,11 @@ class IRLookupSpec extends FirrtlFlatSpec {
         |    out <= UInt(1)
         |""".stripMargin
 
-    val circuit = new firrtl.stage.transforms.Compiler(Seq(Dependency[ExpandWhensAndCheck])).runTransform(
-      CircuitState(parse(input), UnknownForm)
-    ).circuit
+    val circuit = new firrtl.stage.transforms.Compiler(Seq(Dependency[ExpandWhensAndCheck]))
+      .runTransform(
+        CircuitState(parse(input), UnknownForm)
+      )
+      .circuit
     val irLookup = IRLookup(circuit)
     val Test = ModuleTarget("Test", "Test")
     val uint8 = UIntType(IntWidth(8))
@@ -209,7 +220,8 @@ class IRLookupSpec extends FirrtlFlatSpec {
 
     val out = Test.ref("out")
     val outExpr =
-      WRef("out",
+      WRef(
+        "out",
         BundleType(Seq(Field("a", Default, uint8), Field("b", Default, VectorType(uint8, 2)))),
         PortKind,
         SinkFlow
@@ -237,8 +249,10 @@ class IRLookupSpec extends FirrtlFlatSpec {
 
     check(Test.ref("y"), WRef("y", uint8, WireKind, DuplexFlow))
 
-    check(Test.ref("@and#0"),
-      DoPrim(PrimOps.And,
+    check(
+      Test.ref("@and#0"),
+      DoPrim(
+        PrimOps.And,
         Seq(WRef("y", uint8, WireKind, SourceFlow), DoPrim(AsUInt, Seq(SIntLiteral(-1)), Nil, UIntType(IntWidth(1)))),
         Nil,
         uint8
@@ -247,33 +261,34 @@ class IRLookupSpec extends FirrtlFlatSpec {
 
     val child = WRef("child", BundleType(Seq(Field("out", Default, uint8))), InstanceKind, SourceFlow)
     check(Test.ref("child"), child)
-    check(Test.ref("child").field("out"),
-      WSubField(child, "out", uint8, SourceFlow)
-    )
+    check(Test.ref("child").field("out"), WSubField(child, "out", uint8, SourceFlow))
   }
 
   "IRLookup" should "cache expressions" in {
     def mkType(i: Int): String = {
-      if(i == 0) "UInt<8>" else s"{x: ${mkType(i - 1)}}"
+      if (i == 0) "UInt<8>" else s"{x: ${mkType(i - 1)}}"
     }
 
     val depth = 500
 
     val input =
       s"""circuit Test:
-        |  module Test :
-        |    input in: ${mkType(depth)}
-        |    output out: ${mkType(depth)}
-        |    out <= in
-        |""".stripMargin
+         |  module Test :
+         |    input in: ${mkType(depth)}
+         |    output out: ${mkType(depth)}
+         |    out <= in
+         |""".stripMargin
 
-    val circuit = new firrtl.stage.transforms.Compiler(Seq(Dependency[ExpandWhensAndCheck])).runTransform(
-      CircuitState(parse(input), UnknownForm)
-    ).circuit
+    val circuit = new firrtl.stage.transforms.Compiler(Seq(Dependency[ExpandWhensAndCheck]))
+      .runTransform(
+        CircuitState(parse(input), UnknownForm)
+      )
+      .circuit
     val Test = ModuleTarget("Test", "Test")
     val irLookup = IRLookup(circuit)
     def mkReferences(parent: ReferenceTarget, i: Int): Seq[ReferenceTarget] = {
-      if(i == 0) Seq(parent) else {
+      if (i == 0) Seq(parent)
+      else {
         val newParent = parent.field("x")
         newParent +: mkReferences(newParent, i - 1)
       }
diff --git a/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala b/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala
index a0d444b3..e134f6e5 100644
--- a/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala
+++ b/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala
@@ -9,10 +9,10 @@ import firrtl.testutils._
 
 class InstanceGraphTests extends FirrtlFlatSpec {
   private def getEdgeSet(graph: DiGraph[String]): collection.Map[String, collection.Set[String]] = {
-    (graph.getVertices map {v => (v, graph.getEdges(v))}).toMap
+    (graph.getVertices.map { v => (v, graph.getEdges(v)) }).toMap
   }
 
-  behavior of "InstanceGraph"
+  behavior.of("InstanceGraph")
 
   it should "recognize a simple hierarchy" in {
     val input = """
@@ -33,7 +33,13 @@ circuit Top :
 """
     val circuit = ToWorkingIR.run(parse(input))
     val graph = new InstanceGraph(circuit).graph.transformNodes(_.module)
-    getEdgeSet(graph) shouldBe Map("Top" -> Set("Child1", "Child2"), "Child1" -> Set("Child1a", "Child1b"), "Child2" -> Set(), "Child1a" -> Set(), "Child1b" -> Set())
+    getEdgeSet(graph) shouldBe Map(
+      "Top" -> Set("Child1", "Child2"),
+      "Child1" -> Set("Child1a", "Child1b"),
+      "Child2" -> Set(),
+      "Child1a" -> Set(),
+      "Child1b" -> Set()
+    )
   }
 
   it should "find hierarchical instances correctly in disconnected hierarchies" in {
@@ -97,12 +103,20 @@ circuit Top :
 """
     val circuit = ToWorkingIR.run(parse(input))
     val graph = new InstanceGraph(circuit).graph.transformNodes(_.module)
-    getEdgeSet(graph) shouldBe Map("Top" -> Set("Child1"), "Top2" -> Set("Child2", "Child3"), "Child2" -> Set("Child2a", "Child2b"), "Child1" -> Set(), "Child2a" -> Set(), "Child2b" -> Set(), "Child3" -> Set())
+    getEdgeSet(graph) shouldBe Map(
+      "Top" -> Set("Child1"),
+      "Top2" -> Set("Child2", "Child3"),
+      "Child2" -> Set("Child2a", "Child2b"),
+      "Child1" -> Set(),
+      "Child2a" -> Set(),
+      "Child2b" -> Set(),
+      "Child3" -> Set()
+    )
   }
 
   it should "not drop duplicate nodes when they collide as a result of transformNodes" in {
     val input =
-"""circuit Top :
+      """circuit Top :
   module Buzz :
     skip
   module Fizz :
@@ -134,70 +148,70 @@ circuit Top :
   // experience non-determinism
   it should "preserve Module declaration order" in {
     val input = """
-      |circuit Top :
-      |  module Top :
-      |    inst c1 of Child1
-      |    inst c2 of Child2
-      |  module Child1 :
-      |    inst a of Child1a
-      |    inst b of Child1b
-      |    skip
-      |  module Child1a :
-      |    skip
-      |  module Child1b :
-      |    skip
-      |  module Child2 :
-      |    skip
-      |""".stripMargin
+                  |circuit Top :
+                  |  module Top :
+                  |    inst c1 of Child1
+                  |    inst c2 of Child2
+                  |  module Child1 :
+                  |    inst a of Child1a
+                  |    inst b of Child1b
+                  |    skip
+                  |  module Child1a :
+                  |    skip
+                  |  module Child1b :
+                  |    skip
+                  |  module Child2 :
+                  |    skip
+                  |""".stripMargin
     val circuit = ToWorkingIR.run(parse(input))
     val instGraph = new InstanceGraph(circuit)
     val childMap = instGraph.getChildrenInstances
-    childMap.keys.toSeq should equal (Seq("Top", "Child1", "Child1a", "Child1b", "Child2"))
+    childMap.keys.toSeq should equal(Seq("Top", "Child1", "Child1a", "Child1b", "Child2"))
   }
 
   // Note that due to optimized implementations of Map1-4, at least 5 entries are needed to
   // experience non-determinism
   it should "preserve Instance declaration order" in {
     val input = """
-      |circuit Top :
-      |  module Top :
-      |    inst a of Child
-      |    inst b of Child
-      |    inst c of Child
-      |    inst d of Child
-      |    inst e of Child
-      |    inst f of Child
-      |  module Child :
-      |    skip
-      |""".stripMargin
+                  |circuit Top :
+                  |  module Top :
+                  |    inst a of Child
+                  |    inst b of Child
+                  |    inst c of Child
+                  |    inst d of Child
+                  |    inst e of Child
+                  |    inst f of Child
+                  |  module Child :
+                  |    skip
+                  |""".stripMargin
     val circuit = ToWorkingIR.run(parse(input))
     val instGraph = new InstanceGraph(circuit)
     val childMap = instGraph.getChildrenInstances
     val insts = childMap("Top").toSeq.map(_.name)
-    insts should equal (Seq("a", "b", "c", "d", "e", "f"))
+    insts should equal(Seq("a", "b", "c", "d", "e", "f"))
   }
 
   // Note that due to optimized implementations of Map1-4, at least 5 entries are needed to
   // experience non-determinism
   it should "have defined fullHierarchy order" in {
     val input = """
-      |circuit Top :
-      |  module Top :
-      |    inst a of Child
-      |    inst b of Child
-      |    inst c of Child
-      |    inst d of Child
-      |    inst e of Child
-      |  module Child :
-      |    skip
-      |""".stripMargin
+                  |circuit Top :
+                  |  module Top :
+                  |    inst a of Child
+                  |    inst b of Child
+                  |    inst c of Child
+                  |    inst d of Child
+                  |    inst e of Child
+                  |  module Child :
+                  |    skip
+                  |""".stripMargin
     val circuit = ToWorkingIR.run(parse(input))
     val instGraph = new InstanceGraph(circuit)
     val hier = instGraph.fullHierarchy
-    hier.keys.toSeq.map(_.name) should equal (Seq("Top", "a", "b", "c", "d", "e"))
+    hier.keys.toSeq.map(_.name) should equal(Seq("Top", "a", "b", "c", "d", "e"))
   }
 
-  behavior of "InstanceGraph.staticInstanceCount"
+  behavior.of("InstanceGraph.staticInstanceCount")
 
   it should "report that there is one instance of the top module" in {
     val input =
@@ -207,7 +221,7 @@ circuit Top :
          |""".stripMargin
     val iGraph = new InstanceGraph(ToWorkingIR.run(parse(input)))
     val expectedCounts = Map(OfModule("Foo") -> 1)
-    iGraph.staticInstanceCount should be (expectedCounts)
+    iGraph.staticInstanceCount should be(expectedCounts)
   }
 
   it should "report correct number of instances for a sample circuit" in {
@@ -225,10 +239,8 @@ circuit Top :
          |    inst bar2 of Bar
          |""".stripMargin
     val iGraph = new InstanceGraph(ToWorkingIR.run(parse(input)))
-    val expectedCounts = Map(OfModule("Foo") -> 1,
-                             OfModule("Bar") -> 2,
-                             OfModule("Baz") -> 3)
-    iGraph.staticInstanceCount should be (expectedCounts)
+    val expectedCounts = Map(OfModule("Foo") -> 1, OfModule("Bar") -> 2, OfModule("Baz") -> 3)
+    iGraph.staticInstanceCount should be(expectedCounts)
   }
 
   it should "report zero instances for dead modules" in {
@@ -240,12 +252,11 @@ circuit Top :
          |    skip
          |""".stripMargin
     val iGraph = new InstanceGraph(ToWorkingIR.run(parse(input)))
-    val expectedCounts = Map(OfModule("Foo") -> 1,
-                             OfModule("Bar") -> 0)
-    iGraph.staticInstanceCount should be (expectedCounts)
+    val expectedCounts = Map(OfModule("Foo") -> 1, OfModule("Bar") -> 0)
+    iGraph.staticInstanceCount should be(expectedCounts)
   }
 
-  behavior of "Reachable/Unreachable helper methods"
+  behavior.of("Reachable/Unreachable helper methods")
 
   they should "report correct reachable/unreachable counts" in {
     val input =
diff --git a/src/test/scala/firrtlTests/analyses/InstanceKeyGraphSpec.scala b/src/test/scala/firrtlTests/analyses/InstanceKeyGraphSpec.scala
index ec403259..1e486fe4 100644
--- a/src/test/scala/firrtlTests/analyses/InstanceKeyGraphSpec.scala
+++ b/src/test/scala/firrtlTests/analyses/InstanceKeyGraphSpec.scala
@@ -9,10 +9,10 @@ import firrtl.graph.DiGraph
 import firrtl.testutils.FirrtlFlatSpec
 
 class InstanceKeyGraphSpec extends FirrtlFlatSpec {
-  behavior of "InstanceKeyGraph.graph"
+  behavior.of("InstanceKeyGraph.graph")
 
   private def getEdgeSet(graph: DiGraph[String]): collection.Map[String, collection.Set[String]] = {
-    (graph.getVertices map {v => (v, graph.getEdges(v))}).toMap
+    (graph.getVertices.map { v => (v, graph.getEdges(v)) }).toMap
   }
 
   it should "recognize a simple hierarchy" in {
@@ -37,7 +37,10 @@ class InstanceKeyGraphSpec extends FirrtlFlatSpec {
     getEdgeSet(graph) shouldBe Map(
       "Top" -> Set("Child1", "Child2"),
       "Child1" -> Set("Child1a", "Child1b"),
-      "Child2" -> Set(), "Child1a" -> Set(), "Child1b" -> Set())
+      "Child2" -> Set(),
+      "Child1a" -> Set(),
+      "Child1b" -> Set()
+    )
   }
 
   it should "recognize disconnected hierarchies" in {
@@ -69,7 +72,11 @@ class InstanceKeyGraphSpec extends FirrtlFlatSpec {
       "Top" -> Set("Child1"),
       "Top2" -> Set("Child2", "Child3"),
       "Child2" -> Set("Child2a", "Child2b"),
-      "Child1" -> Set(), "Child2a" -> Set(), "Child2b" -> Set(), "Child3" -> Set())
+      "Child1" -> Set(),
+      "Child2a" -> Set(),
+      "Child2b" -> Set(),
+      "Child3" -> Set()
+    )
   }
 
   it should "not drop duplicate nodes when they collide as a result of transformNodes" in {
@@ -101,8 +108,7 @@ class InstanceKeyGraphSpec extends FirrtlFlatSpec {
     g2.getEdges("Fizz") shouldBe Set("Foo", "Bar")
   }
 
-
-  behavior of "InstanceKeyGraph.getChildInstances"
+  behavior.of("InstanceKeyGraph.getChildInstances")
 
   // Note that due to optimized implementations of Map1-4, at least 5 entries are needed to
   // experience non-determinism
@@ -126,7 +132,7 @@ class InstanceKeyGraphSpec extends FirrtlFlatSpec {
     val circuit = parse(input)
     val instGraph = InstanceKeyGraph(circuit)
     val childMap = instGraph.getChildInstances
-    childMap.map(_._1) should equal (Seq("Top", "Child1", "Child1a", "Child1b", "Child2"))
+    childMap.map(_._1) should equal(Seq("Top", "Child1", "Child1a", "Child1b", "Child2"))
   }
 
   // Note that due to optimized implementations of Map1-4, at least 5 entries are needed to
@@ -148,10 +154,10 @@ class InstanceKeyGraphSpec extends FirrtlFlatSpec {
     val instGraph = InstanceKeyGraph(circuit)
     val childMap = instGraph.getChildInstances.toMap
     val insts = childMap("Top").map(_.name)
-    insts should equal (Seq("a", "b", "c", "d", "e", "f"))
+    insts should equal(Seq("a", "b", "c", "d", "e", "f"))
   }
 
-  behavior of "InstanceKeyGraph.moduleOrder"
+  behavior.of("InstanceKeyGraph.moduleOrder")
 
   it should "compute a correct and deterministic module order" in {
     val input = """
@@ -180,10 +186,10 @@ class InstanceKeyGraphSpec extends FirrtlFlatSpec {
     val instGraph = InstanceKeyGraph(circuit)
     val order = instGraph.moduleOrder.map(_.name)
     // Where it has freedom, the instance declaration order will be reversed.
-    order should equal (Seq("Top", "Child3", "Child4", "Child2", "Child1", "Child1b", "Child1a"))
+    order should equal(Seq("Top", "Child3", "Child4", "Child2", "Child1", "Child1b", "Child1a"))
   }
 
-  behavior of "InstanceKeyGraph.findInstancesInHierarchy"
+  behavior.of("InstanceKeyGraph.findInstancesInHierarchy")
 
   it should "find hierarchical instances correctly in disconnected hierarchies" in {
     val input =
@@ -221,7 +227,7 @@ class InstanceKeyGraphSpec extends FirrtlFlatSpec {
     iGraph.findInstancesInHierarchy("Child3") shouldBe Nil
   }
 
-  behavior of "InstanceKeyGraph.staticInstanceCount"
+  behavior.of("InstanceKeyGraph.staticInstanceCount")
 
   it should "report that there is one instance of the top module" in {
     val input =
@@ -231,7 +237,7 @@ class InstanceKeyGraphSpec extends FirrtlFlatSpec {
          |""".stripMargin
     val iGraph = InstanceKeyGraph(parse(input))
     val expectedCounts = Map(OfModule("Foo") -> 1)
-    iGraph.staticInstanceCount should be (expectedCounts)
+    iGraph.staticInstanceCount should be(expectedCounts)
   }
 
   it should "report correct number of instances for a sample circuit" in {
@@ -249,10 +255,8 @@ class InstanceKeyGraphSpec extends FirrtlFlatSpec {
          |    inst bar2 of Bar
          |""".stripMargin
     val iGraph = InstanceKeyGraph(parse(input))
-    val expectedCounts = Map(OfModule("Foo") -> 1,
-      OfModule("Bar") -> 2,
-      OfModule("Baz") -> 3)
-    iGraph.staticInstanceCount should be (expectedCounts)
+    val expectedCounts = Map(OfModule("Foo") -> 1, OfModule("Bar") -> 2, OfModule("Baz") -> 3)
+    iGraph.staticInstanceCount should be(expectedCounts)
   }
 
   it should "report zero instances for dead modules" in {
@@ -264,12 +268,11 @@ class InstanceKeyGraphSpec extends FirrtlFlatSpec {
          |    skip
          |""".stripMargin
     val iGraph = InstanceKeyGraph(parse(input))
-    val expectedCounts = Map(OfModule("Foo") -> 1,
-      OfModule("Bar") -> 0)
-    iGraph.staticInstanceCount should be (expectedCounts)
+    val expectedCounts = Map(OfModule("Foo") -> 1, OfModule("Bar") -> 0)
+    iGraph.staticInstanceCount should be(expectedCounts)
   }
 
-  behavior of "InstanceKeyGraph.getChildInstanceMap"
+  behavior.of("InstanceKeyGraph.getChildInstanceMap")
 
   it should "preserve Module declaration order" in {
     val input = """
@@ -302,15 +305,17 @@ class InstanceKeyGraphSpec extends FirrtlFlatSpec {
     assert(childMap(OfModule("Child1b")).isEmpty)
     assert(childMap(OfModule("Child2")).isEmpty)
 
-    val topInstances = childMap(OfModule("Top")).map { case (k,v) => k.value -> v.value}.toSeq
-    assert(topInstances ==
-      Seq("c1" -> "Child1", "c2" -> "Child2", "c3" -> "Child1", "c4" -> "Child1", "c5" -> "Child1"))
+    val topInstances = childMap(OfModule("Top")).map { case (k, v) => k.value -> v.value }.toSeq
+    assert(
+      topInstances ==
+        Seq("c1" -> "Child1", "c2" -> "Child2", "c3" -> "Child1", "c4" -> "Child1", "c5" -> "Child1")
+    )
 
-    val child1Instance = childMap(OfModule("Child1")).map { case (k,v) => k.value -> v.value}.toSeq
+    val child1Instance = childMap(OfModule("Child1")).map { case (k, v) => k.value -> v.value }.toSeq
     assert(child1Instance == Seq("a" -> "Child1a", "b" -> "Child1b"))
   }
 
-  behavior of "InstanceKeyGraph.fullHierarchy"
+  behavior.of("InstanceKeyGraph.fullHierarchy")
 
   // Note that due to optimized implementations of Map1-4, at least 5 entries are needed to
   // experience non-determinism
@@ -329,10 +334,10 @@ class InstanceKeyGraphSpec extends FirrtlFlatSpec {
 
     val instGraph = InstanceKeyGraph(parse(input))
     val hier = instGraph.fullHierarchy
-    hier.keys.toSeq.map(_.name) should equal (Seq("Top", "a", "b", "c", "d", "e"))
+    hier.keys.toSeq.map(_.name) should equal(Seq("Top", "a", "b", "c", "d", "e"))
   }
 
-  behavior of "Reachable/Unreachable helper methods"
+  behavior.of("Reachable/Unreachable helper methods")
 
   they should "report correct reachable/unreachable counts" in {
     val input =