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authorJack Koenig2018-02-27 18:07:11 -0800
committerGitHub2018-02-27 18:07:11 -0800
commitc7eb1570dfb1c7701ea32d1209982a053f3cec1d (patch)
tree3f509b202d82841c5dad5588d1f953a25d389b44 /src/test/scala/firrtlTests/InferReadWriteSpec.scala
parentb90fc784a1819c1d7905910130a7da022214bc22 (diff)
Refactor Annotations (#721)
- Old Annotation renamed to deprecated LegacyAnnotation - Annotation is now a trait that can be extended - New JsonProtocol for Annotation [de]serialization - Replace AnnotationMap with AnnotationSeq - Deprecate Transform.getMyAnnotations - Update Transforms - Turn on deprecation warnings - Remove deprecated Driver.compile - Make AnnotationTests abstract with Legacy and Json subclasses - Add functionality to convert LegacyAnnotations of built-in annos This will give a noisy warning and is more of a best effort than a robust solution. Fixes #475 Closes #609
Diffstat (limited to 'src/test/scala/firrtlTests/InferReadWriteSpec.scala')
-rw-r--r--src/test/scala/firrtlTests/InferReadWriteSpec.scala12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/test/scala/firrtlTests/InferReadWriteSpec.scala b/src/test/scala/firrtlTests/InferReadWriteSpec.scala
index 82c9d65f..34e228be 100644
--- a/src/test/scala/firrtlTests/InferReadWriteSpec.scala
+++ b/src/test/scala/firrtlTests/InferReadWriteSpec.scala
@@ -71,8 +71,8 @@ circuit sram6t :
T_5 <= io.wdata
""".stripMargin
- val annotationMap = AnnotationMap(Seq(memlib.InferReadWriteAnnotation("sram6t")))
- val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annotationMap)))
+ val annos = Seq(memlib.InferReadWriteAnnotation)
+ val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos))
// Check correctness of firrtl
parse(res.getEmittedCircuit.value)
}
@@ -102,8 +102,8 @@ circuit sram6t :
io.dataOut <= _T_22
""".stripMargin
- val annotationMap = AnnotationMap(Seq(memlib.InferReadWriteAnnotation("sram6t")))
- val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annotationMap)))
+ val annos = Seq(memlib.InferReadWriteAnnotation)
+ val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos))
// Check correctness of firrtl
parse(res.getEmittedCircuit.value)
}
@@ -133,9 +133,9 @@ circuit sram6t :
T_5 <= io.wdata
""".stripMargin
- val annotationMap = AnnotationMap(Seq(memlib.InferReadWriteAnnotation("sram6t")))
+ val annos = Seq(memlib.InferReadWriteAnnotation)
intercept[InferReadWriteCheckException] {
- compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annotationMap)))
+ compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos))
}
}
}