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| author | Schuyler Eldridge | 2019-10-22 00:48:59 -0400 |
|---|---|---|
| committer | GitHub | 2019-10-22 00:48:59 -0400 |
| commit | f5e6e2bc201c6206a705244d8977bda4b83e6efd (patch) | |
| tree | 3e42e57b110beefd6e13457db199d7c3a7d0bd4c /src/test/scala/firrtlTests/ExtModuleTests.scala | |
| parent | b43288d588d04775230456ca85fa231a8cf397fe (diff) | |
| parent | a4cb228161410de4c5ab2029d7756870f32d28b8 (diff) | |
Merge pull request #1204 from freechipsproject/else-if
Emit Verilog else-if for Register Updates
Diffstat (limited to 'src/test/scala/firrtlTests/ExtModuleTests.scala')
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