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| author | Jack Koenig | 2019-12-13 00:01:41 -0800 |
|---|---|---|
| committer | Jack Koenig | 2020-01-07 18:35:44 -0800 |
| commit | e27bb38cf5b3ee8135bf416c2532b2abc2fc5ae4 (patch) | |
| tree | 589e59ef4e2563ca67e695f476ed67a8f8ef5aa5 /src/test/scala/firrtlTests/ExtModuleTests.scala | |
| parent | c16ef85cc76d6693045f1ecb84ad02227bab33c0 (diff) | |
Fix literals cast to Clocks in Print and Stop
Many tools don't except 'always @(posedge 1'h0)' so we assign the
literal to a wire and use that as the posedge target.
Diffstat (limited to 'src/test/scala/firrtlTests/ExtModuleTests.scala')
0 files changed, 0 insertions, 0 deletions