diff options
| author | Jack Koenig | 2019-11-30 01:29:55 -0800 |
|---|---|---|
| committer | Jack Koenig | 2020-01-07 18:35:43 -0800 |
| commit | c16ef85cc76d6693045f1ecb84ad02227bab33c0 (patch) | |
| tree | aeaf4599eddc50790d8e58aeea172a471224014b /src/test/scala/firrtlTests/ExtModuleTests.scala | |
| parent | df48d61c3e1cb476f51762b1f009ecc9391221c6 (diff) | |
Remove unnecessary $signed casts for PrimOps in Verilog Emitter
[skip formal checks]
Adds new InlineCastsTransform to the VerilogEmitter which removes
Statements that do nothing but cast by inlining the cast Expression
Diffstat (limited to 'src/test/scala/firrtlTests/ExtModuleTests.scala')
0 files changed, 0 insertions, 0 deletions