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| author | Chick Markley | 2018-06-06 22:00:40 -0700 |
|---|---|---|
| committer | Jack Koenig | 2018-06-06 22:00:40 -0700 |
| commit | dcdfc467a5f59058b482127340ebef375cec077a (patch) | |
| tree | 5cf582d7df5b382d13571cf72ced308af9b06fb3 /src/test/scala/firrtlTests/ExtModuleTests.scala | |
| parent | 7c49fa1726ab1860fbb3616156467807de2d7e3c (diff) | |
Mechanism to stop verilator from generating VCD file Chisel Issue #808 (#794)
Add optional argument to verilogToCpp to suppress VCD
Diffstat (limited to 'src/test/scala/firrtlTests/ExtModuleTests.scala')
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