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| author | Jack Koenig | 2018-06-06 21:13:24 -0700 |
|---|---|---|
| committer | GitHub | 2018-06-06 21:13:24 -0700 |
| commit | 7c49fa1726ab1860fbb3616156467807de2d7e3c (patch) | |
| tree | f3fd0f149f22811acd6048ad4bb58722351873e3 /src/test/scala/firrtlTests/ExtModuleTests.scala | |
| parent | c9d40a022efc2d4380186912e61c2c91d07e8958 (diff) | |
ConstProp attached wires if there is also a port (#818)
This enables the pattern of attaching "through" a wire to give better
Verilog that also works in Verilator
Use WrappedExpression when combining attaches in ExpandWhens
to ensure no duplication of references in resulting, combined attaches
Diffstat (limited to 'src/test/scala/firrtlTests/ExtModuleTests.scala')
0 files changed, 0 insertions, 0 deletions