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| author | Schuyler Eldridge | 2019-10-16 12:40:08 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-10-22 00:16:26 -0400 |
| commit | 17f7bc04491397e8839a4dab8756c7fa8ac2ce13 (patch) | |
| tree | 7f4148f18ece5f91d152ecaf3b2c58084fffa2b5 /src/test/scala/firrtlTests/ExtModuleTests.scala | |
| parent | b43288d588d04775230456ca85fa231a8cf397fe (diff) | |
Emit Verilog "else if" in register updates
Modifies the Verilog emitter to emit "else if" blocks as opposed to
more deeply nested "else begin if" blocks. This improves the output
Verilog readability.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/test/scala/firrtlTests/ExtModuleTests.scala')
0 files changed, 0 insertions, 0 deletions