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| author | Albert Magyar | 2019-10-16 01:33:30 -0700 |
|---|---|---|
| committer | Albert Magyar | 2019-10-21 10:02:46 -0700 |
| commit | 01b10725163c5bbe239c11f14b6136c737160d34 (patch) | |
| tree | b77e1cfeeb3a8063ad6c88cfc8318ab285af0471 /src/test/scala/firrtlTests/ExtModuleTests.scala | |
| parent | 71d714a252bd027b7f85aa17132ba9fb05153e3a (diff) | |
Add test for #1179: comb-loops from VerilogMemDelays
Diffstat (limited to 'src/test/scala/firrtlTests/ExtModuleTests.scala')
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