diff options
| author | Albert Magyar | 2019-10-16 01:28:04 -0700 |
|---|---|---|
| committer | Albert Magyar | 2019-10-21 10:02:46 -0700 |
| commit | 71d714a252bd027b7f85aa17132ba9fb05153e3a (patch) | |
| tree | 2e5b4bcbced615c6165bf2ca73527ad3704b329f /src/test/scala/firrtlTests/ExtModuleTests.scala | |
| parent | fd981848c7d2a800a15f9acfbf33b57dd1c6225b (diff) | |
Fix write-first mem enable handling in VerilogMemDelays
* Additional refactoring to clean up pass implementation
* Make register names match old scheme to appease CI
Diffstat (limited to 'src/test/scala/firrtlTests/ExtModuleTests.scala')
0 files changed, 0 insertions, 0 deletions