Add missing invalidations to some transforms (#1541)

This adds missing invalidations to four transforms:

  - ExpandConnects
  - RemoveAccesses
  - SplitExpressions
  - VerilogMemDelays

This necessarily updates test cases which expect exact transform
orders to reflect the new order.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

1 files changed, 9 insertions, 4 deletions

diff --git a/src/test/scala/firrtlTests/CustomTransformSpec.scala b/src/test/scala/firrtlTests/CustomTransformSpec.scala
index f1b2045e..ef1dc86d 100644
--- a/src/test/scala/firrtlTests/CustomTransformSpec.scala
+++ b/src/test/scala/firrtlTests/CustomTransformSpec.scala
@@ -167,10 +167,15 @@ class CustomTransformSpec extends FirrtlFlatSpec {
         .containsSlice(expectedSlice) should be (true)
     }
 
-    Seq( (Dependency[LowFirrtlEmitter],      Seq(Forms.LowForm.last)                 ),
-         (Dependency[MinimumVerilogEmitter], Seq(Forms.LowFormMinimumOptimized.last) ),
-         (Dependency[VerilogEmitter],        Seq(Forms.LowFormOptimized.last)        ),
-         (Dependency[SystemVerilogEmitter],  Seq(Forms.LowFormOptimized.last)        )
+    val Seq(low, lowMinOpt, lowOpt) =
+      Seq(Forms.LowForm, Forms.LowFormMinimumOptimized, Forms.LowFormOptimized)
+        .map(target => new firrtl.stage.transforms.Compiler(target))
+        .map(_.flattenedTransformOrder.map(Dependency.fromTransform(_)))
+
+    Seq( (Dependency[LowFirrtlEmitter],      Seq(low.last)      ),
+         (Dependency[MinimumVerilogEmitter], Seq(lowMinOpt.last)),
+         (Dependency[VerilogEmitter],        Seq(lowOpt.last)    ),
+         (Dependency[SystemVerilogEmitter],  Seq(lowOpt.last)   )
     ).foreach((testOrder _).tupled)
   }