Add missing invalidations to some transforms (#1541)

This adds missing invalidations to four transforms:

  - ExpandConnects
  - RemoveAccesses
  - SplitExpressions
  - VerilogMemDelays

This necessarily updates test cases which expect exact transform
orders to reflect the new order.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

2 files changed, 21 insertions, 7 deletions

diff --git a/src/test/scala/firrtlTests/CustomTransformSpec.scala b/src/test/scala/firrtlTests/CustomTransformSpec.scala
index f1b2045e..ef1dc86d 100644
--- a/src/test/scala/firrtlTests/CustomTransformSpec.scala
+++ b/src/test/scala/firrtlTests/CustomTransformSpec.scala
@@ -167,10 +167,15 @@ class CustomTransformSpec extends FirrtlFlatSpec {
         .containsSlice(expectedSlice) should be (true)
     }
 
-    Seq( (Dependency[LowFirrtlEmitter],      Seq(Forms.LowForm.last)                 ),
-         (Dependency[MinimumVerilogEmitter], Seq(Forms.LowFormMinimumOptimized.last) ),
-         (Dependency[VerilogEmitter],        Seq(Forms.LowFormOptimized.last)        ),
-         (Dependency[SystemVerilogEmitter],  Seq(Forms.LowFormOptimized.last)        )
+    val Seq(low, lowMinOpt, lowOpt) =
+      Seq(Forms.LowForm, Forms.LowFormMinimumOptimized, Forms.LowFormOptimized)
+        .map(target => new firrtl.stage.transforms.Compiler(target))
+        .map(_.flattenedTransformOrder.map(Dependency.fromTransform(_)))
+
+    Seq( (Dependency[LowFirrtlEmitter],      Seq(low.last)      ),
+         (Dependency[MinimumVerilogEmitter], Seq(lowMinOpt.last)),
+         (Dependency[VerilogEmitter],        Seq(lowOpt.last)    ),
+         (Dependency[SystemVerilogEmitter],  Seq(lowOpt.last)   )
     ).foreach((testOrder _).tupled)
   }
 
diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
index ea591450..4a7a1700 100644
--- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
+++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
@@ -158,8 +158,11 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
   it should "replicate the old order" in {
     val tm = new TransformManager(Forms.MidForm, Forms.Deduped)
     val patches = Seq(
+      Add(4, Seq(Dependency(firrtl.passes.ResolveFlows))),
+      Add(5, Seq(Dependency(firrtl.passes.ResolveKinds))),
       Add(6, Seq(Dependency(firrtl.passes.ResolveKinds),
-                 Dependency(firrtl.passes.InferTypes))),
+                 Dependency(firrtl.passes.InferTypes),
+                 Dependency(firrtl.passes.ResolveFlows))),
       Del(7),
       Del(8),
       Add(7, Seq(Dependency[firrtl.passes.ExpandWhensAndCheck])),
@@ -184,7 +187,11 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
 
   it should "replicate the old order" in {
     val tm = new TransformManager(Forms.LowFormMinimumOptimized, Forms.LowForm)
-    compare(legacyTransforms(new MinimumLowFirrtlOptimization), tm)
+    val patches = Seq(
+      Add(4, Seq(Dependency(firrtl.passes.ResolveFlows))),
+      Add(5, Seq(Dependency(firrtl.passes.ResolveKinds)))
+    )
+    compare(legacyTransforms(new MinimumLowFirrtlOptimization), tm, patches)
   }
 
   behavior of "LowFirrtlOptimization"
@@ -192,7 +199,9 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
   it should "replicate the old order" in {
     val tm = new TransformManager(Forms.LowFormOptimized, Forms.LowForm)
     val patches = Seq(
-      Add(7, Seq(Dependency(firrtl.passes.Legalize)))
+      Add(6, Seq(Dependency(firrtl.passes.ResolveFlows))),
+      Add(7, Seq(Dependency(firrtl.passes.Legalize))),
+      Add(8, Seq(Dependency(firrtl.passes.ResolveKinds)))
     )
     compare(legacyTransforms(new LowFirrtlOptimization), tm, patches)
   }