Clk2clock - rename the implicit "clk" module input "clock" (#387)

* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.

* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.

1 files changed, 2 insertions, 2 deletions

diff --git a/src/test/scala/firrtlTests/CustomTransformSpec.scala b/src/test/scala/firrtlTests/CustomTransformSpec.scala
index 4a3faf6b..3a20082f 100644
--- a/src/test/scala/firrtlTests/CustomTransformSpec.scala
+++ b/src/test/scala/firrtlTests/CustomTransformSpec.scala
@@ -15,13 +15,13 @@ class CustomTransformSpec extends FirrtlFlatSpec {
     val delayModuleString = """
       |circuit Delay :
       |  module Delay :
-      |    input clk : Clock
+      |    input clock : Clock
       |    input reset : UInt<1>
       |    input a : UInt<32>
       |    input en : UInt<1>
       |    output b : UInt<32>
       |
-      |    reg r : UInt<32>, clk
+      |    reg r : UInt<32>, clock
       |    r <= r
       |    when en :
       |      r <= a