All of src/ formatted with scalafmt

1 files changed, 26 insertions, 26 deletions

diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala
index dcc8b872..2d13c835 100644
--- a/src/test/scala/firrtlTests/ChirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala
@@ -30,49 +30,49 @@ class ChirrtlSpec extends FirrtlFlatSpec {
 
   "Chirrtl memories" should "allow ports with clocks defined after the memory" in {
     val input =
-     """circuit Unit :
-       |  module Unit :
-       |    input clock : Clock
-       |    smem ram : UInt<32>[128]
-       |    node newClock = clock
-       |    infer mport x = ram[UInt(2)], newClock
-       |    x <= UInt(3)
-       |    when UInt(1) :
-       |      infer mport y = ram[UInt(4)], newClock
-       |      y <= UInt(5)
+      """circuit Unit :
+        |  module Unit :
+        |    input clock : Clock
+        |    smem ram : UInt<32>[128]
+        |    node newClock = clock
+        |    infer mport x = ram[UInt(2)], newClock
+        |    x <= UInt(3)
+        |    when UInt(1) :
+        |      infer mport y = ram[UInt(4)], newClock
+        |      y <= UInt(5)
        """.stripMargin
     val circuit = Parser.parse(input.split("\n").toIterator)
-    transforms.foldLeft(CircuitState(circuit, UnknownForm)) {
-      (c: CircuitState, p: Transform) => p.runTransform(c)
+    transforms.foldLeft(CircuitState(circuit, UnknownForm)) { (c: CircuitState, p: Transform) =>
+      p.runTransform(c)
     }
   }
 
   "Chirrtl" should "catch undeclared wires" in {
     val input =
-     """circuit Unit :
-       |  module Unit :
-       |    input clock : Clock
-       |    smem ram : UInt<32>[128]
-       |    node newClock = clock
-       |    infer mport x = ram[UInt(2)], newClock
-       |    x <= UInt(3)
-       |    when UInt(1) :
-       |      infer mport y = ram[UInt(4)], newClock
-       |      y <= z
+      """circuit Unit :
+        |  module Unit :
+        |    input clock : Clock
+        |    smem ram : UInt<32>[128]
+        |    node newClock = clock
+        |    infer mport x = ram[UInt(2)], newClock
+        |    x <= UInt(3)
+        |    when UInt(1) :
+        |      infer mport y = ram[UInt(4)], newClock
+        |      y <= z
        """.stripMargin
     intercept[PassException] {
       val circuit = Parser.parse(input.split("\n").toIterator)
-      transforms.foldLeft(CircuitState(circuit, UnknownForm)) {
-        (c: CircuitState, p: Transform) => p.runTransform(c)
+      transforms.foldLeft(CircuitState(circuit, UnknownForm)) { (c: CircuitState, p: Transform) =>
+        p.runTransform(c)
       }
     }
   }
 
-  behavior of "Uniqueness"
+  behavior.of("Uniqueness")
   for ((description, input) <- CheckSpec.nonUniqueExamples) {
     it should s"be asserted for $description" in {
       assertThrows[CheckHighForm.NotUniqueException] {
-        Seq(ToWorkingIR, CheckHighForm).foldLeft(Parser.parse(input)){ case (c, tx) => tx.run(c) }
+        Seq(ToWorkingIR, CheckHighForm).foldLeft(Parser.parse(input)) { case (c, tx) => tx.run(c) }
       }
     }
   }