Deprecate all mutable methods on RenameMap (#2444)

* Add renamemap.MutableRenameMap which includes these methods without
  deprecation
* Deprecate Stringly typed RenameMap APIs which were accidentally
  undeprecated a while ago

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

2 files changed, 9 insertions, 7 deletions

diff --git a/src/test/scala/firrtl/passes/LowerTypesSpec.scala b/src/test/scala/firrtl/passes/LowerTypesSpec.scala
index 7ca98544..1d15bd70 100644
--- a/src/test/scala/firrtl/passes/LowerTypesSpec.scala
+++ b/src/test/scala/firrtl/passes/LowerTypesSpec.scala
@@ -5,6 +5,7 @@ import firrtl.annotations.{CircuitTarget, IsMember}
 import firrtl.annotations.TargetToken.{Instance, OfModule}
 import firrtl.analyses.InstanceKeyGraph
 import firrtl.{CircuitState, RenameMap, Utils}
+import firrtl.renamemap.MutableRenameMap
 import firrtl.options.Dependency
 import firrtl.stage.TransformManager
 import firrtl.stage.TransformManager.TransformDependency
@@ -252,7 +253,7 @@ class LowerTypesOfInstancesSpec extends AnyFlatSpec with FirrtlMatchers {
     tpe:          String,
     module:       String,
     namespace:    Set[String],
-    otherRenames: RenameMap = RenameMap()
+    otherRenames: MutableRenameMap = MutableRenameMap()
   ): Lower = {
     val ref = firrtl.ir.DefInstance(firrtl.ir.NoInfo, n, module, parseType(tpe))
     val mutableSet = scala.collection.mutable.HashSet[String]() ++ namespace
@@ -298,8 +299,8 @@ class LowerTypesOfInstancesSpec extends AnyFlatSpec with FirrtlMatchers {
       // This is to accommodate the use-case where a port as well as an instance needs to be renames
       // thus requiring a two-stage translation process for reference to the port of the instance.
       // This two-stage translation is only supported through chaining rename maps.
-      val portRenames = RenameMap()
-      val otherRenames = RenameMap()
+      val portRenames = MutableRenameMap()
+      val otherRenames = MutableRenameMap()
 
       // The child module "c" which we assume has the following ports: b : { c : UInt<1>} and b_c : UInt<1>
       val c = CircuitTarget("m").module("c")
@@ -362,7 +363,7 @@ class LowerTypesOfMemorySpec extends AnyFlatSpec {
       writers = w,
       readwriters = rw
     )
-    val renames = RenameMap()
+    val renames = MutableRenameMap()
     val mutableSet = scala.collection.mutable.HashSet[String]() ++ namespace
     val (mems, refs) = DestructTypes.destructMemory(m, mem, mutableSet, renames, Set())
     Lower(mems, refs, renames)
@@ -655,10 +656,10 @@ private object LowerTypesSpecUtils {
     val c = CircuitState(firrtl.Parser.parse(src), Seq())
     typedCompiler.execute(c).circuit.modules.head.ports.head.tpe
   }
-  case class DestructResult(fields: Seq[String], renameMap: RenameMap)
+  case class DestructResult(fields: Seq[String], renameMap: MutableRenameMap)
   def destruct(n: String, tpe: String, namespace: Set[String]): DestructResult = {
     val ref = firrtl.ir.Field(n, firrtl.ir.Default, parseType(tpe))
-    val renames = RenameMap()
+    val renames = MutableRenameMap()
     val mutableSet = scala.collection.mutable.HashSet[String]() ++ namespace
     val res = DestructTypes.destruct(m, ref, mutableSet, renames, Set())
     DestructResult(resultToFieldSeq(res), renames)
diff --git a/src/test/scala/firrtl/testutils/FirrtlSpec.scala b/src/test/scala/firrtl/testutils/FirrtlSpec.scala
index 53a8e1e3..f37f6860 100644
--- a/src/test/scala/firrtl/testutils/FirrtlSpec.scala
+++ b/src/test/scala/firrtl/testutils/FirrtlSpec.scala
@@ -19,6 +19,7 @@ import firrtl.stage.{FirrtlFileAnnotation, InfoModeAnnotation, RunFirrtlTransfor
 import firrtl.analyses.{GetNamespace, ModuleNamespaceAnnotation}
 import firrtl.annotations._
 import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation, RenameModules}
+import firrtl.renamemap.MutableRenameMap
 import firrtl.util.BackendCompilationUtilities
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
@@ -64,7 +65,7 @@ object RenameTop extends Transform {
       case m => m
     }
 
-    val renames = RenameMap()
+    val renames = MutableRenameMap()
     renames.record(CircuitTarget(c.main), CircuitTarget(newTopName))
     state.copy(circuit = c.copy(main = newTopName, modules = modulesx), renames = Some(renames))
   }