diff options
17 files changed, 375 insertions, 174 deletions
diff --git a/src/main/scala/firrtl/RenameMap.scala b/src/main/scala/firrtl/RenameMap.scala index d39d8106..1f05fa5a 100644 --- a/src/main/scala/firrtl/RenameMap.scala +++ b/src/main/scala/firrtl/RenameMap.scala @@ -7,21 +7,15 @@ import firrtl.RenameMap.IllegalRenameException import firrtl.analyses.InstanceKeyGraph import firrtl.annotations.TargetToken.{Field, Index, Instance, OfModule} import TargetUtils.{instKeyPathToTarget, unfoldInstanceTargets} +import firrtl.renamemap._ import scala.collection.mutable +import scala.annotation.nowarn object RenameMap { - def apply(map: collection.Map[Named, Seq[Named]]): RenameMap = { - val rm = new RenameMap - rm.addMap(map) - rm - } + def apply(map: collection.Map[Named, Seq[Named]]): RenameMap = MutableRenameMap.fromNamed(map) - def create(map: collection.Map[CompleteTarget, Seq[CompleteTarget]]): RenameMap = { - val rm = new RenameMap - rm.recordAll(map) - rm - } + def create(map: collection.Map[CompleteTarget, Seq[CompleteTarget]]): RenameMap = MutableRenameMap(map) /** RenameMap factory for simple renaming of instances * @@ -72,16 +66,11 @@ object RenameMap { underlying(fromx) = List(tox) } } - new RenameMap(underlying) + new MutableRenameMap(underlying) } /** Initialize a new RenameMap */ - def apply(): RenameMap = new RenameMap - - // This is a private internal API for transforms where the .distinct operation is very expensive - // (eg. LowerTypes). The onus is on the user of this API to be very careful and not inject - // duplicates. This is a bad, hacky API that no one should use - private[firrtl] def noDistinct(): RenameMap = new RenameMap(doDistinct = false) + def apply(): RenameMap = new MutableRenameMap abstract class RenameTargetException(reason: String) extends Exception(reason) case class IllegalRenameException(reason: String) extends RenameTargetException(reason) @@ -96,14 +85,22 @@ object RenameMap { * @define noteDistinct @note Rename to/tos will be made distinct */ // TODO This should probably be refactored into immutable and mutable versions -final class RenameMap private ( - val underlying: mutable.HashMap[CompleteTarget, Seq[CompleteTarget]] = - mutable.HashMap[CompleteTarget, Seq[CompleteTarget]](), - val chained: Option[RenameMap] = None, +sealed trait RenameMap { + + protected def _underlying: mutable.HashMap[CompleteTarget, Seq[CompleteTarget]] + + protected def _chained: Option[RenameMap] + // This is a private internal API for transforms where the .distinct operation is very expensive // (eg. LowerTypes). The onus is on the user of this API to be very careful and not inject // duplicates. This is a bad, hacky API that no one should use - doDistinct: Boolean = true) { + protected def doDistinct: Boolean + + @deprecated("This should never have been public", "FIRRTL 1.5") + def underlying: mutable.HashMap[CompleteTarget, Seq[CompleteTarget]] = _underlying + + @deprecated("This should never have been public", "FIRRTL 1.5") + def chained: Option[RenameMap] = _chained /** Chain a [[RenameMap]] with this [[RenameMap]] * @param next the map to chain with this map @@ -111,10 +108,10 @@ final class RenameMap private ( * $noteDistinct */ def andThen(next: RenameMap): RenameMap = { - if (next.chained.isEmpty) { - new RenameMap(next.underlying, chained = Some(this)) + if (next._chained.isEmpty) { + new MutableRenameMap(next._underlying, Some(this)) } else { - new RenameMap(next.underlying, chained = next.chained.map(this.andThen(_))) + new MutableRenameMap(next._underlying, next._chained.map(this.andThen(_))) } } @@ -125,6 +122,7 @@ final class RenameMap private ( * $noteSelfRename * $noteDistinct */ + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") def record(from: CircuitTarget, to: CircuitTarget): Unit = completeRename(from, Seq(to)) /** Record that the from [[firrtl.annotations.CircuitTarget CircuitTarget]] is renamed to another sequence of @@ -134,6 +132,7 @@ final class RenameMap private ( * $noteSelfRename * $noteDistinct */ + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") def record(from: CircuitTarget, tos: Seq[CircuitTarget]): Unit = completeRename(from, tos) /** Record that the from [[firrtl.annotations.IsMember Member]] is renamed to another [[firrtl.annotations.IsMember @@ -143,6 +142,7 @@ final class RenameMap private ( * $noteSelfRename * $noteDistinct */ + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") def record(from: IsMember, to: IsMember): Unit = completeRename(from, Seq(to)) /** Record that the from [[firrtl.annotations.IsMember IsMember]] is renamed to another sequence of @@ -152,6 +152,7 @@ final class RenameMap private ( * $noteSelfRename * $noteDistinct */ + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") def record(from: IsMember, tos: Seq[IsMember]): Unit = completeRename(from, tos) /** Records that the keys in map are also renamed to their corresponding value seqs. Only @@ -162,7 +163,10 @@ final class RenameMap private ( * $noteSelfRename * $noteDistinct */ - def recordAll(map: collection.Map[CompleteTarget, Seq[CompleteTarget]]): Unit = + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") + def recordAll(map: collection.Map[CompleteTarget, Seq[CompleteTarget]]): Unit = _recordAll(map) + + protected def _recordAll(map: collection.Map[CompleteTarget, Seq[CompleteTarget]]): Unit = map.foreach { case (from: IsComponent, tos: Seq[_]) => completeRename(from, tos) case (from: IsModule, tos: Seq[_]) => completeRename(from, tos) @@ -173,7 +177,8 @@ final class RenameMap private ( /** Records that a [[firrtl.annotations.CompleteTarget CompleteTarget]] is deleted * @param name */ - def delete(name: CompleteTarget): Unit = underlying(name) = Seq.empty + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") + def delete(name: CompleteTarget): Unit = _underlying(name) = Seq.empty /** Renames a [[firrtl.annotations.CompleteTarget CompleteTarget]] * @param t target to rename @@ -204,33 +209,38 @@ final class RenameMap private ( * @return */ def ++(renameMap: RenameMap): RenameMap = { - val newChained = if (chained.nonEmpty && renameMap.chained.nonEmpty) { - Some(chained.get ++ renameMap.chained.get) + val newChained = if (_chained.nonEmpty && renameMap._chained.nonEmpty) { + Some(_chained.get ++ renameMap._chained.get) } else { - chained.map(_.copy()) + _chained.map(_._copy()) } - new RenameMap(underlying = underlying ++ renameMap.getUnderlying, chained = newChained) + new MutableRenameMap(_underlying ++ renameMap._underlying, newChained) } /** Creates a deep copy of this [[RenameMap]] */ - def copy(chained: Option[RenameMap] = chained): RenameMap = { - val ret = new RenameMap(chained = chained.map(_.copy())) - ret.recordAll(underlying) + @deprecated("RenameMap is becoming more function-like, this shouldn't be necessary", "FIRRTL 1.5") + def copy(chained: Option[RenameMap] = _chained): RenameMap = _copy(chained) + + private def _copy(chained: Option[RenameMap] = _chained): RenameMap = { + val ret = new MutableRenameMap(_chained = _chained.map(_._copy())) + ret.recordAll(_underlying) ret } /** Returns the underlying map of rename information * @return */ - def getUnderlying: collection.Map[CompleteTarget, Seq[CompleteTarget]] = underlying + @deprecated("This should never have been public", "FIRRTL 1.5") + def getUnderlying: collection.Map[CompleteTarget, Seq[CompleteTarget]] = _underlying /** @return Whether this [[RenameMap]] has collected any changes */ - def hasChanges: Boolean = underlying.nonEmpty + def hasChanges: Boolean = _underlying.nonEmpty + @deprecated("RenameMap is becoming more function-like and is not invertible", "FIRRTL 1.5") def getReverseRenameMap: RenameMap = { val reverseMap = mutable.HashMap[CompleteTarget, Seq[CompleteTarget]]() - underlying.keysIterator.foreach { key => + _underlying.keysIterator.foreach { key => apply(key).foreach { v => reverseMap(v) = key +: reverseMap.getOrElse(v, Nil) } @@ -238,12 +248,12 @@ final class RenameMap private ( RenameMap.create(reverseMap) } - def keys: Iterator[CompleteTarget] = underlying.keysIterator + @deprecated("This should never have been public", "FIRRTL 1.5") + def keys: Iterator[CompleteTarget] = _underlying.keysIterator - /** Serialize the underlying remapping of keys to new targets - * @return + /** Visualize the [[RenameMap]] */ - def serialize: String = underlying.map { + def serialize: String = _underlying.map { case (k, v) => k.serialize + "=>" + v.map(_.serialize).mkString(", ") }.mkString("\n") @@ -280,8 +290,8 @@ final class RenameMap private ( * @return Optionally return sequence of targets that key remaps to */ private def completeGet(key: CompleteTarget): Option[Seq[CompleteTarget]] = { - if (chained.nonEmpty) { - val chainedRet = chained.get.completeGet(key).getOrElse(Seq(key)) + if (_chained.nonEmpty) { + val chainedRet = _chained.get.completeGet(key).getOrElse(Seq(key)) if (chainedRet.isEmpty) { Some(chainedRet) } else { @@ -329,8 +339,8 @@ final class RenameMap private ( private def referenceGet(errors: mutable.ArrayBuffer[String])(key: ReferenceTarget): Option[Seq[IsComponent]] = { def traverseTokens(key: ReferenceTarget): Option[Seq[IsComponent]] = traverseTokensCache.getOrElseUpdate( key, { - if (underlying.contains(key)) { - Some(underlying(key).flatMap { + if (_underlying.contains(key)) { + Some(_underlying(key).flatMap { case comp: IsComponent => Some(comp) case other => errors += s"reference ${key.targetParent} cannot be renamed to a non-component ${other}" @@ -402,7 +412,7 @@ final class RenameMap private ( private def instanceGet(errors: mutable.ArrayBuffer[String])(key: InstanceTarget): Option[Seq[IsModule]] = { def traverseLeft(key: InstanceTarget): Option[Seq[IsModule]] = traverseLeftCache.getOrElseUpdate( key, { - val getOpt = underlying.get(key) + val getOpt = _underlying.get(key) if (getOpt.nonEmpty) { getOpt.map(_.flatMap { @@ -447,7 +457,7 @@ final class RenameMap private ( } private def circuitGet(errors: mutable.ArrayBuffer[String])(key: CircuitTarget): Seq[CircuitTarget] = { - underlying + _underlying .get(key) .map(_.flatMap { case c: CircuitTarget => Some(c) @@ -459,7 +469,7 @@ final class RenameMap private ( } private def moduleGet(errors: mutable.ArrayBuffer[String])(key: ModuleTarget): Option[Seq[IsModule]] = { - underlying + _underlying .get(key) .map(_.flatMap { case mod: IsModule => Some(mod) @@ -668,14 +678,14 @@ final class RenameMap private ( * @param from * @param tos */ - private def completeRename(from: CompleteTarget, tos: Seq[CompleteTarget]): Unit = { + protected def completeRename(from: CompleteTarget, tos: Seq[CompleteTarget]): Unit = { tos.foreach { recordSensitivity(from, _) } - val existing = underlying.getOrElse(from, Vector.empty) + val existing = _underlying.getOrElse(from, Vector.empty) val updated = { val all = (existing ++ tos) if (doDistinct) all.distinct else all } - underlying(from) = updated + _underlying(from) = updated traverseTokensCache.clear() traverseHierarchyCache.clear() traverseLeftCache.clear() @@ -684,20 +694,28 @@ final class RenameMap private ( /* DEPRECATED ACCESSOR/SETTOR METHODS WITH [[firrtl.ir.Named Named]] */ + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") def rename(from: Named, to: Named): Unit = rename(from, Seq(to)) + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") def rename(from: Named, tos: Seq[Named]): Unit = recordAll(Map(from.toTarget -> tos.map(_.toTarget))) + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") def rename(from: ComponentName, to: ComponentName): Unit = record(from, to) + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") def rename(from: ComponentName, tos: Seq[ComponentName]): Unit = record(from, tos.map(_.toTarget)) - def delete(name: CircuitName): Unit = underlying(name) = Seq.empty + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") + def delete(name: CircuitName): Unit = _underlying(name) = Seq.empty - def delete(name: ModuleName): Unit = underlying(name) = Seq.empty + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") + def delete(name: ModuleName): Unit = _underlying(name) = Seq.empty - def delete(name: ComponentName): Unit = underlying(name) = Seq.empty + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") + def delete(name: ComponentName): Unit = _underlying(name) = Seq.empty + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") def addMap(map: collection.Map[Named, Seq[Named]]): Unit = recordAll(map.map { case (key, values) => (Target.convertNamed2Target(key), values.map(Target.convertNamed2Target)) @@ -727,17 +745,20 @@ final class RenameMap private ( /** Sets mutable state to record current module we are visiting * @param module */ + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") def setModule(module: String): Unit = moduleName = module /** Sets mutable state to record current circuit we are visiting * @param circuit */ + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") def setCircuit(circuit: String): Unit = circuitName = circuit /** Records how a reference maps to a new reference * @param from * @param to */ + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") def rename(from: String, to: String): Unit = rename(from, Seq(to)) /** Records how a reference maps to a new reference @@ -745,6 +766,7 @@ final class RenameMap private ( * @param from * @param tos */ + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") def rename(from: String, tos: Seq[String]): Unit = { val mn = ModuleName(moduleName, CircuitName(circuitName)) val fromName = ComponentName(from, mn).toTarget @@ -756,6 +778,7 @@ final class RenameMap private ( * The reference's root module and circuit are determined by whomever called setModule or setCircuit last * @param name */ + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") def delete(name: String): Unit = { Target(Some(circuitName), Some(moduleName), AnnotationUtils.toSubComponents(name)).getComplete match { case Some(t: CircuitTarget) => delete(t) @@ -768,5 +791,92 @@ final class RenameMap private ( * The reference's root module and circuit are determined by whomever called setModule or setCircuit last * @param names */ + @deprecated("Use firrtl.renamemap.MutableRenameMap for recording renames", "FIRRTL 1.5") def delete(names: Seq[String]): Unit = names.foreach(delete(_)) } + +// This must be in same file as RenameMap because RenameMap is sealed +package object renamemap { + object MutableRenameMap { + def fromNamed(map: collection.Map[Named, Seq[Named]]): MutableRenameMap = { + val rm = new MutableRenameMap + rm.addMap(map) + rm + } + + def apply(map: collection.Map[CompleteTarget, Seq[CompleteTarget]]): MutableRenameMap = { + val rm = new MutableRenameMap + rm.recordAll(map) + rm + } + + /** Initialize a new RenameMap */ + def apply(): MutableRenameMap = new MutableRenameMap + + // This is a private internal API for transforms where the .distinct operation is very expensive + // (eg. LowerTypes). The onus is on the user of this API to be very careful and not inject + // duplicates. This is a bad, hacky API that no one should use + private[firrtl] def noDistinct(): MutableRenameMap = new MutableRenameMap(doDistinct = false) + } + + // Override deprecated methods so they aren't deprecated when using this class + final class MutableRenameMap private[firrtl] ( + protected val _underlying: mutable.HashMap[CompleteTarget, Seq[CompleteTarget]] = + mutable.HashMap[CompleteTarget, Seq[CompleteTarget]](), + protected val _chained: Option[RenameMap] = None, + protected val doDistinct: Boolean = true) + extends RenameMap { + + override def record(from: CircuitTarget, to: CircuitTarget): Unit = completeRename(from, Seq(to)) + + override def record(from: CircuitTarget, tos: Seq[CircuitTarget]): Unit = completeRename(from, tos) + + override def record(from: IsMember, to: IsMember): Unit = completeRename(from, Seq(to)) + + override def record(from: IsMember, tos: Seq[IsMember]): Unit = completeRename(from, tos) + + override def recordAll(map: collection.Map[CompleteTarget, Seq[CompleteTarget]]): Unit = + super._recordAll(map) + + override def delete(name: CompleteTarget): Unit = _underlying(name) = Seq.empty + + override def rename(from: Named, to: Named): Unit = rename(from, Seq(to)) + + override def rename(from: Named, tos: Seq[Named]): Unit = recordAll(Map(from.toTarget -> tos.map(_.toTarget))) + + override def rename(from: ComponentName, to: ComponentName): Unit = record(from, to) + + override def rename(from: ComponentName, tos: Seq[ComponentName]): Unit = record(from, tos.map(_.toTarget)) + + override def delete(name: CircuitName): Unit = _underlying(name) = Seq.empty + + override def delete(name: ModuleName): Unit = _underlying(name) = Seq.empty + + override def delete(name: ComponentName): Unit = _underlying(name) = Seq.empty + + override def addMap(map: collection.Map[Named, Seq[Named]]): Unit = + recordAll(map.map { + case (key, values) => (Target.convertNamed2Target(key), values.map(Target.convertNamed2Target)) + }) + + // These are overridden to change the deprecation warning + + @deprecated("Use type-safe rename methods instead", "FIRRTL 1.5") + override def setModule(module: String): Unit = super.setModule(module) + + @deprecated("Use type-safe rename methods instead", "FIRRTL 1.5") + override def setCircuit(circuit: String): Unit = super.setCircuit(circuit) + + @deprecated("Use type-safe rename methods instead", "FIRRTL 1.5") + override def rename(from: String, to: String): Unit = super.rename(from, to) + + @deprecated("Use type-safe rename methods instead", "FIRRTL 1.5") + override def rename(from: String, tos: Seq[String]): Unit = super.rename(from, tos) + + @deprecated("Use type-safe delete methods instead", "FIRRTL 1.5") + override def delete(name: String): Unit = super.delete(name) + + @deprecated("Use type-safe delete methods instead", "FIRRTL 1.5") + override def delete(names: Seq[String]): Unit = super.delete(names) + } +} diff --git a/src/main/scala/firrtl/annotations/transforms/CleanupNamedTargets.scala b/src/main/scala/firrtl/annotations/transforms/CleanupNamedTargets.scala index 28f50993..8635d9ed 100644 --- a/src/main/scala/firrtl/annotations/transforms/CleanupNamedTargets.scala +++ b/src/main/scala/firrtl/annotations/transforms/CleanupNamedTargets.scala @@ -7,6 +7,7 @@ import firrtl.annotations.{CircuitTarget, ModuleTarget, MultiTargetAnnotation, R import firrtl.ir import firrtl.options.{Dependency, PreservesAll} import firrtl.traversals.Foreachers._ +import firrtl.renamemap.MutableRenameMap import scala.collection.immutable.{Set => ISet} @@ -31,7 +32,7 @@ class CleanupNamedTargets extends Transform with DependencyAPIMigration { statement: ir.Statement )( implicit references: ISet[ReferenceTarget], - renameMap: RenameMap, + renameMap: MutableRenameMap, module: ModuleTarget ): Unit = statement match { case ir.DefInstance(_, a, b, _) if references(module.instOf(a, b).asReference) => @@ -43,7 +44,7 @@ class CleanupNamedTargets extends Transform with DependencyAPIMigration { module: ir.DefModule )( implicit references: ISet[ReferenceTarget], - renameMap: RenameMap, + renameMap: MutableRenameMap, circuit: CircuitTarget ): Unit = { implicit val mTarget = circuit.module(module.name) @@ -60,7 +61,7 @@ class CleanupNamedTargets extends Transform with DependencyAPIMigration { case a: ReferenceTarget => a }.toSet - implicit val renameMap = RenameMap() + implicit val renameMap = MutableRenameMap() implicit val cTarget = CircuitTarget(state.circuit.main) diff --git a/src/main/scala/firrtl/annotations/transforms/EliminateTargetPaths.scala b/src/main/scala/firrtl/annotations/transforms/EliminateTargetPaths.scala index 104aafc3..83bea253 100644 --- a/src/main/scala/firrtl/annotations/transforms/EliminateTargetPaths.scala +++ b/src/main/scala/firrtl/annotations/transforms/EliminateTargetPaths.scala @@ -10,6 +10,7 @@ import firrtl.annotations.analysis.DuplicationHelper import firrtl.annotations._ import firrtl.ir._ import firrtl.{AnnotationSeq, CircuitState, DependencyAPIMigration, FirrtlInternalException, RenameMap, Transform} +import firrtl.renamemap.MutableRenameMap import firrtl.stage.Forms import firrtl.transforms.DedupedResult import firrtl.transforms.DedupAnnotationsTransform @@ -45,7 +46,12 @@ case class NoSuchTargetException(message: String) extends FirrtlInternalExceptio object EliminateTargetPaths { - def renameModules(c: Circuit, toRename: Map[String, String], renameMap: RenameMap): Circuit = { + @deprecated("Use version that accepts renamemap.MutableRenameMap", "FIRRTL 1.5") + def renameModules(c: Circuit, toRename: Map[String, String], renameMap: RenameMap): Circuit = + // Cast is safe because RenameMap is sealed trait, MutableRenameMap is only subclass + renameModules(c, toRename, renameMap.asInstanceOf[MutableRenameMap]) + + def renameModules(c: Circuit, toRename: Map[String, String], renameMap: MutableRenameMap): Circuit = { val ct = CircuitTarget(c.main) val cx = if (toRename.contains(c.main)) { renameMap.record(ct, CircuitTarget(toRename(c.main))) @@ -159,7 +165,7 @@ class EliminateTargetPaths extends Transform with DependencyAPIMigration { lazy val finalModuleSet = finalModuleList.map { case a: DefModule => a.name }.toSet // Records how targets have been renamed - val renameMap = RenameMap() + val renameMap = MutableRenameMap() /* Foreach target, calculate the pathless version and only rename targets that are instantiated. Additionally, rename * module targets @@ -264,7 +270,7 @@ class EliminateTargetPaths extends Transform with DependencyAPIMigration { val cache = mutable.Map.empty[String, Boolean] mod => cache.getOrElseUpdate(mod, iGraph.findInstancesInHierarchy(mod).size == 1) } - val firstRenameMap = RenameMap() + val firstRenameMap = MutableRenameMap() val nonSingletonTargets = targets.foldRight(Seq.empty[IsMember]) { case (t: IsComponent, acc) if t.asPath.nonEmpty => val origPath = t.asPath @@ -298,11 +304,13 @@ class EliminateTargetPaths extends Transform with DependencyAPIMigration { val (newCircuit, nextRenameMap, newAnnos) = run(state.circuit, nonSingletonTargets, iGraph) - val renameMap = + val renameMap: MutableRenameMap = if (firstRenameMap.hasChanges) { - firstRenameMap.andThen(nextRenameMap) + // Cast is safe because RenameMap is sealed trait, MutableRenameMap is only subclass + firstRenameMap.andThen(nextRenameMap).asInstanceOf[MutableRenameMap] } else { - nextRenameMap + // Cast is safe because RenameMap is sealed trait, MutableRenameMap is only subclass + nextRenameMap.asInstanceOf[MutableRenameMap] } val iGraphx = InstanceKeyGraph(newCircuit) diff --git a/src/main/scala/firrtl/backends/experimental/smt/StutteringClockTransform.scala b/src/main/scala/firrtl/backends/experimental/smt/StutteringClockTransform.scala index 5db39ac9..534db217 100644 --- a/src/main/scala/firrtl/backends/experimental/smt/StutteringClockTransform.scala +++ b/src/main/scala/firrtl/backends/experimental/smt/StutteringClockTransform.scala @@ -11,6 +11,7 @@ import firrtl.passes.PassException import firrtl.stage.Forms import firrtl.stage.TransformManager.TransformDependency import firrtl.transforms.PropagatePresetAnnotations +import firrtl.renamemap.MutableRenameMap import scala.collection.mutable @@ -94,7 +95,7 @@ class StutteringClockTransform extends Transform with DependencyAPIMigration { // rename clocks to clock enable signals val mRef = CircuitTarget(state.circuit.main).module(main.name) - val renameMap = RenameMap() + val renameMap = MutableRenameMap() scan.clockToEnable.foreach { case (clk, en) => renameMap.record(mRef.ref(clk), mRef.ref(en.name)) diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala index 85eb7b51..e2105ff2 100644 --- a/src/main/scala/firrtl/passes/Inline.scala +++ b/src/main/scala/firrtl/passes/Inline.scala @@ -11,6 +11,7 @@ import firrtl.analyses.InstanceKeyGraph import firrtl.graph.{DiGraph, MutableDiGraph} import firrtl.stage.{Forms, RunFirrtlTransformAnnotation} import firrtl.options.{RegisteredTransform, ShellOption} +import firrtl.renamemap.MutableRenameMap // Datastructures import scala.collection.mutable @@ -184,7 +185,7 @@ class InlineInstances extends Transform with DependencyAPIMigration with Registe prefix: String, ns: Namespace, renames: mutable.HashMap[String, String], - renameMap: RenameMap + renameMap: MutableRenameMap )(s: Statement ): Statement = { def onName(ofModuleOpt: Option[String])(name: String): String = { @@ -276,10 +277,10 @@ class InlineInstances extends Transform with DependencyAPIMigration with Registe indexMap match { case a if a.isEmpty => - (Map.empty[(OfModule, Instance), RenameMap], Seq.empty[RenameMap]) + (Map.empty[(OfModule, Instance), MutableRenameMap], Seq.empty[MutableRenameMap]) case a => val maxIdx = indexMap.values.max - val resultSeq = Seq.fill(maxIdx + 1)(RenameMap()) + val resultSeq = Seq.fill(maxIdx + 1)(MutableRenameMap()) val resultMap = indexMap.mapValues(idx => resultSeq(maxIdx - idx)) (resultMap, resultSeq) } @@ -367,7 +368,8 @@ class InlineInstances extends Transform with DependencyAPIMigration with Registe Some(m.map(onStmt(ModuleName(m.name, CircuitName(c.main))))) }) - val renames = renamesSeq.reduceLeftOption(_ andThen _) + // Upcast so reduce works (andThen returns RenameMap) + val renames = (renamesSeq: Seq[RenameMap]).reduceLeftOption(_ andThen _) val cleanedAnnos = annos.filterNot { case InlineAnnotation(_) => true diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala index 7ba320d0..976741fd 100644 --- a/src/main/scala/firrtl/passes/LowerTypes.scala +++ b/src/main/scala/firrtl/passes/LowerTypes.scala @@ -28,6 +28,7 @@ import firrtl.{ import firrtl.ir._ import firrtl.options.Dependency import firrtl.stage.TransformManager.TransformDependency +import firrtl.renamemap.MutableRenameMap import scala.annotation.tailrec import scala.collection.mutable @@ -80,7 +81,7 @@ object LowerTypes extends Transform with DependencyAPIMigration { // writers. Unfortunately, when you have lots of renames, this is very expensive // performance-wise. We use a private internal API that does not run .distinct to improve // performance, but we must be careful to not insert any duplicates. - val refRenameMap = RenameMap.noDistinct() + val refRenameMap = MutableRenameMap.noDistinct() val resultAndRenames = state.circuit.modules.map(m => onModule(c, m, memInitByModule.getOrElse(m.name, Seq()), refRenameMap)) val result = state.circuit.copy(modules = resultAndRenames.map(_._1)) @@ -100,7 +101,7 @@ object LowerTypes extends Transform with DependencyAPIMigration { c: CircuitTarget, m: DefModule, memoryInit: Seq[MemoryInitAnnotation], - renameMap: RenameMap + renameMap: MutableRenameMap ): (DefModule, Map[Instance, Instance], Seq[MemoryInitAnnotation]) = { val ref = c.module(m.name) @@ -123,7 +124,7 @@ object LowerTypes extends Transform with DependencyAPIMigration { private def lowerPorts( ref: ModuleTarget, m: DefModule, - renameMap: RenameMap + renameMap: MutableRenameMap ): (DefModule, Seq[(String, Seq[Reference])]) = { val namespace = mutable.HashSet[String]() ++ m.ports.map(_.name) val loweredPortsAndRefs = m.ports.flatMap { p => @@ -225,7 +226,7 @@ private class LoweringSymbolTable extends SymbolTable { // Lowers types and keeps track of references to lowered types. private class LoweringTable( table: LoweringSymbolTable, - renameMap: RenameMap, + renameMap: MutableRenameMap, m: ModuleTarget, portNameToExprs: Seq[(String, Seq[Reference])]) { private val portNames: Set[String] = portNameToExprs.map(_._2.head.name).toSet @@ -284,7 +285,7 @@ private object DestructTypes { m: ModuleTarget, ref: Field, namespace: Namespace, - renameMap: RenameMap, + renameMap: MutableRenameMap, reserved: Set[String] ): Seq[(Field, String)] = { // field renames (uniquify) are computed bottom up @@ -349,7 +350,7 @@ private object DestructTypes { m: ModuleTarget, mem: DefMemory, namespace: Namespace, - renameMap: RenameMap, + renameMap: MutableRenameMap, reserved: Set[String] ): (Seq[DefMemory], Seq[(String, SubField)]) = { // Uniquify the lowered memory names: When memories get split up into ground types, the access order is changes. @@ -425,7 +426,7 @@ private object DestructTypes { private def recordRenames( fieldToRefs: Seq[(Field, Seq[ReferenceTarget])], - renameMap: RenameMap, + renameMap: MutableRenameMap, parent: ParentRef ): Unit = { // TODO: if we group by ReferenceTarget, we could reduce the number of calls to `record`. Is it worth it? diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala index f8511820..d181e6ac 100644 --- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala +++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala @@ -9,6 +9,7 @@ import firrtl.ir._ import firrtl.Utils._ import firrtl.Mappers._ import firrtl.options.Dependency +import firrtl.renamemap.MutableRenameMap case class MPort(name: String, clk: Expression) case class MPorts(readers: ArrayBuffer[MPort], writers: ArrayBuffer[MPort], readwriters: ArrayBuffer[MPort]) @@ -78,6 +79,7 @@ object RemoveCHIRRTL extends Transform with DependencyAPIMigration { s.map(collect_smems_and_mports(mports, smems)) } + @deprecated("This should never have been public", "FIRRTL 1.5") def collect_refs( mports: MPortMap, smems: SeqMemSet, @@ -86,6 +88,18 @@ object RemoveCHIRRTL extends Transform with DependencyAPIMigration { raddrs: AddrMap, renames: RenameMap )(s: Statement + ): Statement = + // Cast is safe because RenameMap is sealed trait, MutableRenameMap is only subclass + collect_refs(mports, smems, types, refs, raddrs, renames.asInstanceOf[MutableRenameMap])(s) + + private def collect_refs( + mports: MPortMap, + smems: SeqMemSet, + types: MPortTypeMap, + refs: DataRefMap, + raddrs: AddrMap, + renames: MutableRenameMap + )(s: Statement ): Statement = s match { case sx: CDefMemory => types(sx.name) = sx.tpe @@ -285,7 +299,12 @@ object RemoveCHIRRTL extends Transform with DependencyAPIMigration { } } - def remove_chirrtl_m(renames: RenameMap)(m: DefModule): DefModule = { + @deprecated("This should never have been public", "FIRRTL 1.5") + def remove_chirrtl_m(renames: RenameMap)(m: DefModule): DefModule = + // Cast is safe because RenameMap is sealed trait, MutableRenameMap is only subclass + remove_chirrtl_m(renames.asInstanceOf[MutableRenameMap])(m) + + private def remove_chirrtl_m(renames: MutableRenameMap)(m: DefModule): DefModule = { val mports = new MPortMap val smems = new SeqMemSet val types = new MPortTypeMap @@ -299,7 +318,7 @@ object RemoveCHIRRTL extends Transform with DependencyAPIMigration { def execute(state: CircuitState): CircuitState = { val c = state.circuit - val renames = RenameMap() + val renames = MutableRenameMap() renames.setCircuit(c.main) val result = c.copy(modules = c.modules.map(remove_chirrtl_m(renames))) state.copy(circuit = result, renames = Some(renames)) diff --git a/src/main/scala/firrtl/passes/ZeroWidth.scala b/src/main/scala/firrtl/passes/ZeroWidth.scala index 80eeab12..ab1cf7bb 100644 --- a/src/main/scala/firrtl/passes/ZeroWidth.scala +++ b/src/main/scala/firrtl/passes/ZeroWidth.scala @@ -5,6 +5,7 @@ package firrtl.passes import firrtl.PrimOps._ import firrtl.ir._ import firrtl._ +import firrtl.renamemap.MutableRenameMap import firrtl.Mappers._ import firrtl.options.Dependency @@ -143,7 +144,7 @@ object ZeroWidth extends Transform with DependencyAPIMigration { case _ => e.map(onExp) } } - private def onStmt(renames: RenameMap)(s: Statement): Statement = s match { + private def onStmt(renames: MutableRenameMap)(s: Statement): Statement = s match { case d @ DefWire(info, name, tpe) => renames.delete(getRemoved(d)) removeZero(tpe) match { @@ -181,7 +182,7 @@ object ZeroWidth extends Transform with DependencyAPIMigration { } case sx => sx.map(onStmt(renames)).map(onExp) } - private def onModule(renames: RenameMap)(m: DefModule): DefModule = { + private def onModule(renames: MutableRenameMap)(m: DefModule): DefModule = { renames.setModule(m.name) // For each port, record deleted subcomponents m.ports.foreach { p => renames.delete(getRemoved(p)) } @@ -200,7 +201,7 @@ object ZeroWidth extends Transform with DependencyAPIMigration { // run executeEmptyMemStmt first to remove zero-width memories // then run InferTypes to update widths for addr, en, clk, etc val c = InferTypes.run(executeEmptyMemStmt(state).circuit) - val renames = RenameMap() + val renames = MutableRenameMap() renames.setCircuit(c.main) val result = c.copy(modules = c.modules.map(onModule(renames))) CircuitState(result, outputForm, state.annotations, Some(renames)) diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala index 35a765f8..cb824996 100644 --- a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala +++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala @@ -12,6 +12,7 @@ import firrtl.passes.MemPortUtils.{MemPortMap, Modules} import firrtl.passes.memlib.MemTransformUtils._ import firrtl.passes.wiring._ import firrtl.stage.Forms +import firrtl.renamemap.MutableRenameMap import scala.collection.mutable.ListBuffer @@ -244,7 +245,7 @@ class ReplaceMemMacros extends Transform with DependencyAPIMigration { memPortMap: MemPortMap, memMods: Modules, annotatedMemoriesBuffer: ListBuffer[DefAnnotatedMemory], - renameMap: RenameMap, + renameMap: MutableRenameMap, circuit: String )(s: Statement ): Statement = s match { @@ -282,7 +283,7 @@ class ReplaceMemMacros extends Transform with DependencyAPIMigration { nameMap: NameMap, memMods: Modules, annotatedMemoriesBuffer: ListBuffer[DefAnnotatedMemory], - renameMap: RenameMap, + renameMap: MutableRenameMap, circuit: String )(m: DefModule ) = { @@ -299,7 +300,7 @@ class ReplaceMemMacros extends Transform with DependencyAPIMigration { val memMods = new Modules val nameMap = new NameMap c.modules.map(m => m.map(constructNameMap(namespace, nameMap, m.name))) - val renameMap = RenameMap() + val renameMap = MutableRenameMap() val modules = c.modules.map(updateMemMods(namespace, nameMap, memMods, annotatedMemoriesBuffer, renameMap, c.main)) state.copy( circuit = c.copy(modules = modules ++ memMods), diff --git a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala index 41ffd2be..a622feb4 100644 --- a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala +++ b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala @@ -11,6 +11,7 @@ import firrtl.analyses.InstanceKeyGraph import firrtl.Mappers._ import firrtl.Utils.{kind, throwInternalError} import firrtl.MemoizedHash._ +import firrtl.renamemap.MutableRenameMap import firrtl.backends.experimental.smt.random.DefRandom import firrtl.options.{Dependency, RegisteredTransform, ShellOption} @@ -213,7 +214,7 @@ class DeadCodeElimination extends Transform with RegisteredTransform with Depend instMap: collection.Map[String, String], deadNodes: collection.Set[LogicNode], moduleMap: collection.Map[String, DefModule], - renames: RenameMap, + renames: MutableRenameMap, topName: String, doTouchExtMods: Set[String] )(mod: DefModule @@ -346,7 +347,7 @@ class DeadCodeElimination extends Transform with RegisteredTransform with Depend val liveNodes = depGraph.reachableFrom(circuitSink) + circuitSink val deadNodes = depGraph.getVertices -- liveNodes - val renames = RenameMap() + val renames = MutableRenameMap() renames.setCircuit(c.main) // As we delete deadCode, we will delete ports from Modules and somtimes complete modules diff --git a/src/main/scala/firrtl/transforms/Dedup.scala b/src/main/scala/firrtl/transforms/Dedup.scala index 2fb98224..373066c8 100644 --- a/src/main/scala/firrtl/transforms/Dedup.scala +++ b/src/main/scala/firrtl/transforms/Dedup.scala @@ -13,6 +13,7 @@ import firrtl.Utils.{kind, splitRef, throwInternalError} import firrtl.annotations.transforms.DupedResult import firrtl.annotations.TargetToken.{Instance, OfModule} import firrtl.options.{HasShellOptions, ShellOption} +import firrtl.renamemap.MutableRenameMap import logger.LazyLogging import scala.annotation.tailrec @@ -123,7 +124,7 @@ class DedupModules extends Transform with DependencyAPIMigration { ): (Circuit, RenameMap, AnnotationSeq) = { // RenameMap - val componentRenameMap = RenameMap() + val componentRenameMap = MutableRenameMap() componentRenameMap.setCircuit(c.main) // Maps module name to corresponding dedup module @@ -161,12 +162,12 @@ class DedupModules extends Transform with DependencyAPIMigration { logger.debug(s"[Dedup] $from -> ${to.name}") ct.module(from).asInstanceOf[CompleteTarget] -> Seq(ct.module(to.name)) } - val moduleRenameMap = RenameMap() + val moduleRenameMap = MutableRenameMap() moduleRenameMap.recordAll(map) // Build instanceify renaming map val instanceGraph = InstanceKeyGraph(c) - val instanceify = RenameMap() + val instanceify = MutableRenameMap() val moduleName2Index = c.modules .map(_.name) .zipWithIndex @@ -337,6 +338,18 @@ object DedupModules extends LazyLogging { module.map(onPort).map(onStmt) } + @deprecated("Use version that accepts renamemap.MutableRenameMap", "FIRRTL 1.5") + def dedupInstances( + top: CircuitTarget, + originalModule: String, + moduleMap: Map[String, DefModule], + name2name: Map[String, String], + renameMap: RenameMap + ): DefModule = + // Cast is safe because RenameMap is sealed trait, MutableRenameMap is only concrete class that + // can be instantiated + dedupInstances(top, originalModule, moduleMap, name2name, renameMap.asInstanceOf[MutableRenameMap]) + /** Dedup a module's instances based on dedup map * * Will fixes up module if deduped instance's ports are differently named @@ -353,7 +366,7 @@ object DedupModules extends LazyLogging { originalModule: String, moduleMap: Map[String, DefModule], name2name: Map[String, String], - renameMap: RenameMap + renameMap: MutableRenameMap ): DefModule = { val module = moduleMap(originalModule) @@ -481,11 +494,22 @@ object DedupModules extends LazyLogging { } val tag2all = hashToNames.map { case (hash, names) => hashToTag(hash) -> names.toSet } - val tagMap = RenameMap() + val tagMap = MutableRenameMap() moduleNameToTag.foreach { case (name, tag) => tagMap.record(top.module(name), top.module(tag)) } (tag2all, tagMap) } + @deprecated("Use version that accepts renamemap.MutableRenameMap", "FIRRTL 1.5") + def deduplicate( + circuit: Circuit, + noDedups: Set[String], + previousDupResults: Map[String, String], + renameMap: RenameMap + ): Map[String, DefModule] = + // Cast is safe because RenameMap is sealed trait, MutableRenameMap is only concrete class that + // can be instantiated + deduplicate(circuit, noDedups, previousDupResults, renameMap.asInstanceOf[MutableRenameMap]) + /** Deduplicate * @param circuit Circuit * @param noDedups list of modules to not dedup @@ -496,7 +520,7 @@ object DedupModules extends LazyLogging { circuit: Circuit, noDedups: Set[String], previousDupResults: Map[String, String], - renameMap: RenameMap + renameMap: MutableRenameMap ): Map[String, DefModule] = { val (moduleMap, moduleLinearization) = { @@ -587,10 +611,20 @@ object DedupModules extends LazyLogging { refs.toIndexedSeq } + @deprecated("Use version that accepts renamemap.MutableRenameMap", "FIRRTL 1.5") def computeRenameMap( originalNames: IndexedSeq[ReferenceTarget], dedupedNames: IndexedSeq[ReferenceTarget], renameMap: RenameMap + ): Unit = + // Cast is safe because RenameMap is sealed trait, MutableRenameMap is only concrete class that + // can be instantiated + computeRenameMap(originalNames, dedupedNames, renameMap.asInstanceOf[MutableRenameMap]) + + def computeRenameMap( + originalNames: IndexedSeq[ReferenceTarget], + dedupedNames: IndexedSeq[ReferenceTarget], + renameMap: MutableRenameMap ): Unit = { originalNames.zip(dedupedNames).foreach { diff --git a/src/main/scala/firrtl/transforms/ManipulateNames.scala b/src/main/scala/firrtl/transforms/ManipulateNames.scala index 4a796e58..3596b7e6 100644 --- a/src/main/scala/firrtl/transforms/ManipulateNames.scala +++ b/src/main/scala/firrtl/transforms/ManipulateNames.scala @@ -5,6 +5,7 @@ package firrtl.transforms import firrtl._ import firrtl.analyses.InstanceKeyGraph import firrtl.Mappers._ +import firrtl.renamemap.MutableRenameMap import firrtl.annotations.{ CircuitTarget, @@ -24,6 +25,7 @@ import scala.collection.mutable import scala.reflect.ClassTag /** Base trait for annotations that control the behavior of transforms that sub-class ManipulateNames + * * @see [[ManipulateNamesBlocklistAnnotation]] * @see [[ManipulateNamesAllowlistAnnotation]] * @define noteLocalTargets All targets must be local. Name modification in a non-local target (e.g., a node in a @@ -141,7 +143,7 @@ case class ManipulateNamesAllowlistResultAnnotation[A <: ManipulateNames[_]]( */ private class RenameDataStructure( circuit: ir.Circuit, - val renames: RenameMap, + val renames: MutableRenameMap, val block: Target => Boolean, val allow: Target => Boolean) { @@ -399,6 +401,16 @@ abstract class ManipulateNames[A <: ManipulateNames[_]: ClassTag] extends Transf .map(onStatement(_: ir.Statement, r, moduleTarget)) } + @deprecated("Use version that accepts renamemap.MutableRenameMap", "FIRRTL 1.5") + def run( + c: ir.Circuit, + renames: RenameMap, + block: Target => Boolean, + allow: Target => Boolean + ): ir.Circuit = + // Cast is safe because RenameMap is sealed trait, MutableRenameMap is only subclass + run(c, renames.asInstanceOf[MutableRenameMap], block, allow) + /** Manipulate all names in a circuit * * @param c an input circuit @@ -409,7 +421,7 @@ abstract class ManipulateNames[A <: ManipulateNames[_]: ClassTag] extends Transf */ def run( c: ir.Circuit, - renames: RenameMap, + renames: MutableRenameMap, block: Target => Boolean, allow: Target => Boolean ): ir.Circuit = { @@ -485,7 +497,7 @@ abstract class ManipulateNames[A <: ManipulateNames[_]: ClassTag] extends Transf } } - val renames = RenameMap() + val renames = MutableRenameMap() val circuitx = run(state.circuit, renames, block, allow) val annotationsx = state.annotations.flatMap { diff --git a/src/main/scala/firrtl/transforms/SimplifyMems.scala b/src/main/scala/firrtl/transforms/SimplifyMems.scala index 92e19f7e..90c26efc 100644 --- a/src/main/scala/firrtl/transforms/SimplifyMems.scala +++ b/src/main/scala/firrtl/transforms/SimplifyMems.scala @@ -10,6 +10,7 @@ import firrtl.options.Dependency import firrtl.passes._ import firrtl.passes.memlib._ import firrtl.stage.Forms +import firrtl.renamemap.MutableRenameMap import scala.collection.mutable import AnalysisUtils._ @@ -29,7 +30,12 @@ class SimplifyMems extends Transform with DependencyAPIMigration { case _ => false } - def onModule(c: Circuit, renames: RenameMap)(m: DefModule): DefModule = { + @deprecated("Use version that accepts renamemap.MutableRenameMap", "FIRRTL 1.5") + def onModule(c: Circuit, renames: RenameMap)(m: DefModule): DefModule = + // Cast is safe because RenameMap is sealed trait and MutableRenameMap is only subclass + onModule(c, renames.asInstanceOf[MutableRenameMap])(m) + + def onModule(c: Circuit, renames: MutableRenameMap)(m: DefModule): DefModule = { val moduleNS = Namespace(m) val connects = getConnects(m) val memAdapters = new mutable.LinkedHashMap[String, DefWire] @@ -86,7 +92,7 @@ class SimplifyMems extends Transform with DependencyAPIMigration { override def execute(state: CircuitState): CircuitState = { val c = state.circuit - val renames = RenameMap() + val renames = MutableRenameMap() state.copy(circuit = c.map(onModule(c, renames)), renames = Some(renames)) } } diff --git a/src/test/scala/firrtl/passes/LowerTypesSpec.scala b/src/test/scala/firrtl/passes/LowerTypesSpec.scala index 7ca98544..1d15bd70 100644 --- a/src/test/scala/firrtl/passes/LowerTypesSpec.scala +++ b/src/test/scala/firrtl/passes/LowerTypesSpec.scala @@ -5,6 +5,7 @@ import firrtl.annotations.{CircuitTarget, IsMember} import firrtl.annotations.TargetToken.{Instance, OfModule} import firrtl.analyses.InstanceKeyGraph import firrtl.{CircuitState, RenameMap, Utils} +import firrtl.renamemap.MutableRenameMap import firrtl.options.Dependency import firrtl.stage.TransformManager import firrtl.stage.TransformManager.TransformDependency @@ -252,7 +253,7 @@ class LowerTypesOfInstancesSpec extends AnyFlatSpec with FirrtlMatchers { tpe: String, module: String, namespace: Set[String], - otherRenames: RenameMap = RenameMap() + otherRenames: MutableRenameMap = MutableRenameMap() ): Lower = { val ref = firrtl.ir.DefInstance(firrtl.ir.NoInfo, n, module, parseType(tpe)) val mutableSet = scala.collection.mutable.HashSet[String]() ++ namespace @@ -298,8 +299,8 @@ class LowerTypesOfInstancesSpec extends AnyFlatSpec with FirrtlMatchers { // This is to accommodate the use-case where a port as well as an instance needs to be renames // thus requiring a two-stage translation process for reference to the port of the instance. // This two-stage translation is only supported through chaining rename maps. - val portRenames = RenameMap() - val otherRenames = RenameMap() + val portRenames = MutableRenameMap() + val otherRenames = MutableRenameMap() // The child module "c" which we assume has the following ports: b : { c : UInt<1>} and b_c : UInt<1> val c = CircuitTarget("m").module("c") @@ -362,7 +363,7 @@ class LowerTypesOfMemorySpec extends AnyFlatSpec { writers = w, readwriters = rw ) - val renames = RenameMap() + val renames = MutableRenameMap() val mutableSet = scala.collection.mutable.HashSet[String]() ++ namespace val (mems, refs) = DestructTypes.destructMemory(m, mem, mutableSet, renames, Set()) Lower(mems, refs, renames) @@ -655,10 +656,10 @@ private object LowerTypesSpecUtils { val c = CircuitState(firrtl.Parser.parse(src), Seq()) typedCompiler.execute(c).circuit.modules.head.ports.head.tpe } - case class DestructResult(fields: Seq[String], renameMap: RenameMap) + case class DestructResult(fields: Seq[String], renameMap: MutableRenameMap) def destruct(n: String, tpe: String, namespace: Set[String]): DestructResult = { val ref = firrtl.ir.Field(n, firrtl.ir.Default, parseType(tpe)) - val renames = RenameMap() + val renames = MutableRenameMap() val mutableSet = scala.collection.mutable.HashSet[String]() ++ namespace val res = DestructTypes.destruct(m, ref, mutableSet, renames, Set()) DestructResult(resultToFieldSeq(res), renames) diff --git a/src/test/scala/firrtl/testutils/FirrtlSpec.scala b/src/test/scala/firrtl/testutils/FirrtlSpec.scala index 53a8e1e3..f37f6860 100644 --- a/src/test/scala/firrtl/testutils/FirrtlSpec.scala +++ b/src/test/scala/firrtl/testutils/FirrtlSpec.scala @@ -19,6 +19,7 @@ import firrtl.stage.{FirrtlFileAnnotation, InfoModeAnnotation, RunFirrtlTransfor import firrtl.analyses.{GetNamespace, ModuleNamespaceAnnotation} import firrtl.annotations._ import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation, RenameModules} +import firrtl.renamemap.MutableRenameMap import firrtl.util.BackendCompilationUtilities import org.scalatest.flatspec.AnyFlatSpec import org.scalatest.matchers.should.Matchers @@ -64,7 +65,7 @@ object RenameTop extends Transform { case m => m } - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(CircuitTarget(c.main), CircuitTarget(newTopName)) state.copy(circuit = c.copy(main = newTopName, modules = modulesx), renames = Some(renames)) } diff --git a/src/test/scala/firrtlTests/RenameMapSpec.scala b/src/test/scala/firrtlTests/MutableRenameMapSpec.scala index bebeb0bf..f8997b36 100644 --- a/src/test/scala/firrtlTests/RenameMapSpec.scala +++ b/src/test/scala/firrtlTests/MutableRenameMapSpec.scala @@ -3,13 +3,14 @@ package firrtlTests import firrtl.RenameMap +import firrtl.renamemap.MutableRenameMap import firrtl.RenameMap.IllegalRenameException import firrtl.annotations._ import firrtl.annotations.TargetToken.{Instance, OfModule} import firrtl.analyses.InstanceKeyGraph import firrtl.testutils._ -class RenameMapSpec extends FirrtlFlatSpec { +class MutableRenameMapSpec extends FirrtlFlatSpec { val cir = CircuitTarget("Top") val cir2 = CircuitTarget("Pot") val cir3 = CircuitTarget("Cir3") @@ -31,64 +32,64 @@ class RenameMapSpec extends FirrtlFlatSpec { behavior.of("RenameMap") it should "return None if it does not rename something" in { - val renames = RenameMap() + val renames = MutableRenameMap() renames.get(modA) should be(None) renames.get(foo) should be(None) } it should "return a Seq of renamed things if it does rename something" in { - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(foo, bar) renames.get(foo) should be(Some(Seq(bar))) } it should "allow something to be renamed to multiple things" in { - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(foo, bar) renames.record(foo, fizz) renames.get(foo) should be(Some(Seq(bar, fizz))) } it should "allow something to be renamed to nothing (ie. deleted)" in { - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(foo, Seq()) renames.get(foo) should be(Some(Seq())) } it should "return None if something is renamed to itself" in { - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(foo, foo) renames.get(foo) should be(None) } it should "allow targets to change module" in { - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(foo, fooB) renames.get(foo) should be(Some(Seq(fooB))) } it should "rename targets if their module is renamed" in { - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(modA, modB) renames.get(foo) should be(Some(Seq(fooB))) renames.get(bar) should be(Some(Seq(barB))) } it should "not rename already renamed targets if the module of the target is renamed" in { - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(modA, modB) renames.record(foo, bar) renames.get(foo) should be(Some(Seq(bar))) } it should "rename modules if their circuit is renamed" in { - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(cir, cir2) renames.get(modA) should be(Some(Seq(modA2))) } it should "rename targets if their circuit is renamed" in { - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(cir, cir2) renames.get(foo) should be(Some(Seq(foo2))) } @@ -105,50 +106,50 @@ class RenameMapSpec extends FirrtlFlatSpec { val Middle_l_a = Middle.instOf("l", "Leaf").ref("a") it should "rename targets if modules in the path are renamed" in { - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(Middle, Middle2) renames.get(Top_m) should be(Some(Seq(Top.instOf("m", "Middle2")))) } it should "rename only the instance if instance and module in the path are renamed" in { - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(Middle, Middle2) renames.record(Top.instOf("m", "Middle"), Top.instOf("m2", "Middle")) renames.get(Top_m) should be(Some(Seq(Top.instOf("m2", "Middle")))) } it should "rename targets if instance in the path are renamed" in { - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(Top.instOf("m", "Middle"), Top.instOf("m2", "Middle")) renames.get(Top_m) should be(Some(Seq(Top.instOf("m2", "Middle")))) } it should "rename targets if instance and ofmodule in the path are renamed" in { - val renames = RenameMap() + val renames = MutableRenameMap() val Top_m2 = Top.instOf("m2", "Middle2") renames.record(Top_m, Top_m2) renames.get(Top_m) should be(Some(Seq(Top_m2))) } it should "properly do nothing if no remaps" in { - val renames = RenameMap() + val renames = MutableRenameMap() renames.get(Top_m_l_a) should be(None) } it should "properly rename if leaf is inlined" in { - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(Middle_l_a, Middle_la) renames.get(Top_m_l_a) should be(Some(Seq(Top_m_la))) } it should "properly rename if middle is inlined" in { - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(Top_m_l, Top.instOf("m_l", "Leaf")) renames.get(Top_m_l_a) should be(Some(Seq(Top.instOf("m_l", "Leaf").ref("a")))) } it should "properly rename if leaf and middle are inlined" in { - val renames = RenameMap() + val renames = MutableRenameMap() val inlined = Top.ref("m_l_a") renames.record(Top_m_l_a, inlined) renames.record(Top_m_l, Nil) @@ -158,7 +159,7 @@ class RenameMapSpec extends FirrtlFlatSpec { it should "quickly rename a target with a long path" in { (0 until 50 by 10).foreach { endIdx => - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(TopCircuit.module("Y0"), TopCircuit.module("X0")) val deepTarget = (0 until endIdx) .foldLeft(Top: IsModule) { (t, idx) => @@ -171,7 +172,7 @@ class RenameMapSpec extends FirrtlFlatSpec { } it should "rename only once with multiple renames" in { - val renames = RenameMap() + val renames = MutableRenameMap() val Middle2 = cir.module("Middle2") renames.record(Middle, Middle2) renames.record(Middle.ref("l"), Middle.ref("lx")) @@ -183,7 +184,7 @@ class RenameMapSpec extends FirrtlFlatSpec { val Middle_i = Middle.ref("i") val Middle_o_f = Middle.ref("o").field("f") val Middle_i_f = Middle.ref("i").field("f") - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(Middle_o, Middle_i) renames.get(Middle_o_f) should be(Some(Seq(Middle_i_f))) } @@ -191,7 +192,7 @@ class RenameMapSpec extends FirrtlFlatSpec { it should "rename instances with same ofModule" in { val Middle_o = Middle.instOf("o", "O") val Middle_i = Middle.instOf("i", "O") - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(Middle_o, Middle_i) renames.get(Middle.instOf("o", "O")) should be(Some(Seq(Middle.instOf("i", "O")))) } @@ -199,7 +200,7 @@ class RenameMapSpec extends FirrtlFlatSpec { it should "not treat references as instances targets" in { val Middle_o = Middle.ref("o") val Middle_i = Middle.ref("i") - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(Middle_o, Middle_i) renames.get(Middle.instOf("o", "O")) should be(None) } @@ -221,7 +222,7 @@ class RenameMapSpec extends FirrtlFlatSpec { val fromN = from val tosN = tos.mkString(", ") //it should s"error if a $fromN is renamed to $tosN" in { - val renames = RenameMap() + val renames = MutableRenameMap() for (to <- tos) { (from, to) match { case (f: CircuitTarget, t: CircuitTarget) => renames.record(f, t) @@ -237,7 +238,7 @@ class RenameMapSpec extends FirrtlFlatSpec { } it should "not error if a circular rename occurs" in { - val renames = RenameMap() + val renames = MutableRenameMap() val top = CircuitTarget("Top") renames.record(top.module("A"), top.module("B").instOf("c", "C")) renames.record(top.module("B"), top.module("A").instOf("c", "C")) @@ -247,7 +248,7 @@ class RenameMapSpec extends FirrtlFlatSpec { } it should "not error if a swapping rename occurs" in { - val renames = RenameMap() + val renames = MutableRenameMap() val top = CircuitTarget("Top") renames.record(top.module("A"), top.module("B")) renames.record(top.module("B"), top.module("A")) @@ -256,7 +257,7 @@ class RenameMapSpec extends FirrtlFlatSpec { } it should "error if a reference is renamed to a module and vice versa" in { - val renames = RenameMap() + val renames = MutableRenameMap() val top = CircuitTarget("Top") renames.record(top.module("A").ref("ref"), top.module("B")) renames.record(top.module("C"), top.module("D").ref("ref")) @@ -270,7 +271,7 @@ class RenameMapSpec extends FirrtlFlatSpec { } it should "error if we rename an instance's ofModule into a non-module" in { - val renames = RenameMap() + val renames = MutableRenameMap() val top = CircuitTarget("Top") renames.record(top.module("C"), top.module("D").ref("x")) @@ -280,7 +281,7 @@ class RenameMapSpec extends FirrtlFlatSpec { } it should "error if path is renamed into a non-path" ignore { - val renames = RenameMap() + val renames = MutableRenameMap() val top = CircuitTarget("Top") renames.record(top.module("E").instOf("f", "F"), top.module("E").ref("g")) @@ -303,7 +304,7 @@ class RenameMapSpec extends FirrtlFlatSpec { val lowered2 = aggregate.copy(ref = "agg_field2") // simulating LowerTypes transform - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(subField1, lowered1) renames.record(subField2, lowered2) renames.record(aggregate, Seq(lowered1, lowered2)) @@ -326,7 +327,7 @@ class RenameMapSpec extends FirrtlFlatSpec { val oldAgg = mod.ref("foo").setPathTarget(path) val newAgg = mod.ref("bar").setPathTarget(path) - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(oldAgg, newAgg) val testRef = oldAgg.field("field") @@ -345,7 +346,7 @@ class RenameMapSpec extends FirrtlFlatSpec { val oldRef = modA.ref("oldRef").setPathTarget(path) val newRef = modA.ref("newRef").setPathTarget(path) - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(oldRef, newRef) val testRef = oldRef.addHierarchy("B", "b") @@ -364,7 +365,7 @@ class RenameMapSpec extends FirrtlFlatSpec { val oldAgg = modA.ref("oldAgg").setPathTarget(path).field("field1") val newAgg = modA.ref("newAgg").setPathTarget(path) - val renames = RenameMap() + val renames = MutableRenameMap() renames.record(oldAgg, newAgg) val testRef = oldAgg.addHierarchy("B", "b").field("field2") @@ -432,7 +433,7 @@ class RenameMapSpec extends FirrtlFlatSpec { val from4 = modC.ref("ref") val to4 = modC.ref("refref") - val renames1 = RenameMap() + val renames1 = MutableRenameMap() renames1.record(from1, to1) renames1.record(from2, to2) renames1.record(from3, to3) @@ -452,7 +453,7 @@ class RenameMapSpec extends FirrtlFlatSpec { ) } - val renames2 = RenameMap() + val renames2 = MutableRenameMap() renames2.record(from2, to2) renames2.record(from3, to3) renames2.record(from4, to4) @@ -471,7 +472,7 @@ class RenameMapSpec extends FirrtlFlatSpec { ) } - val renames3 = RenameMap() + val renames3 = MutableRenameMap() renames3.record(from3, to3) renames3.record(from4, to4) @@ -492,7 +493,7 @@ class RenameMapSpec extends FirrtlFlatSpec { it should "correctly handle renaming of modules to instances" in { val cir = CircuitTarget("Top") - val renames = RenameMap() + val renames = MutableRenameMap() val from = cir.module("C") val to = cir.module("D").instOf("e", "E").instOf("f", "F") renames.record(from, to) @@ -506,7 +507,7 @@ class RenameMapSpec extends FirrtlFlatSpec { it should "correctly handle renaming of paths and components at the same time" in { val cir = CircuitTarget("Top") - val renames = RenameMap() + val renames = MutableRenameMap() val from = cir.module("C").ref("foo").field("bar") val to = cir.module("D").instOf("e", "E").instOf("f", "F").ref("foo").field("foo") renames.record(from, to) @@ -528,7 +529,7 @@ class RenameMapSpec extends FirrtlFlatSpec { it should "error if an instance is renamed to a ReferenceTarget" in { val top = CircuitTarget("Top").module("Top") - val renames = RenameMap() + val renames = MutableRenameMap() val from = top.instOf("a", "A") val to = top.ref("b") renames.record(from, to) @@ -539,7 +540,7 @@ class RenameMapSpec extends FirrtlFlatSpec { it should "not allow renaming of instances even if there is a matching reference rename" in { val top = CircuitTarget("Top").module("Top") - val renames = RenameMap() + val renames = MutableRenameMap() val from = top.ref("a") val to = top.ref("b") renames.record(from, to) @@ -549,12 +550,12 @@ class RenameMapSpec extends FirrtlFlatSpec { it should "correctly chain renames together" in { val top = CircuitTarget("Top") - val renames1 = RenameMap() + val renames1 = MutableRenameMap() val from1 = top.module("A") val to1 = top.module("Top").instOf("b", "B") renames1.record(from1, to1) - val renames2 = RenameMap() + val renames2 = MutableRenameMap() val from2 = top.module("B") val to2 = top.module("B1") renames2.record(from2, to2) @@ -577,11 +578,11 @@ class RenameMapSpec extends FirrtlFlatSpec { val modB = top.module("B") val modB1 = top.module("B1") - val renames1 = RenameMap() + val renames1 = MutableRenameMap() renames1.delete(modA) renames1.record(modB, modB1) - val renames2 = RenameMap() + val renames2 = MutableRenameMap() renames2.record(modA, modA1) renames2.delete(modB1) @@ -605,11 +606,11 @@ class RenameMapSpec extends FirrtlFlatSpec { val modC = top.module("C") val modC1 = top.module("C1") - val renames1 = RenameMap() + val renames1 = MutableRenameMap() renames1.record(modA, modA1) renames1.record(modC, modC1) - val renames2 = RenameMap() + val renames2 = MutableRenameMap() renames2.record(modA, modA2) renames2.record(modB, modB1) @@ -633,10 +634,10 @@ class RenameMapSpec extends FirrtlFlatSpec { val oldRef = inlineMod.ref("bar") val prefixRef = inlineMod.ref("foo") - val renames1 = RenameMap() + val renames1 = MutableRenameMap() renames1.record(inlineInst, inlineMod) - val renames2 = RenameMap() + val renames2 = MutableRenameMap() renames2.record(oldRef, prefixRef) renames1.andThen(renames2) @@ -648,10 +649,10 @@ class RenameMapSpec extends FirrtlFlatSpec { val oldRef = inlineMod.ref("bar") val prefixRef = inlineMod.ref("foo") - val renames1 = RenameMap() + val renames1 = MutableRenameMap() renames1.record(inlineInst, inlineMod) - val renames2 = RenameMap() + val renames2 = MutableRenameMap() renames2.record(oldRef, prefixRef) renames1.andThen(renames2) @@ -680,13 +681,13 @@ class RenameMapSpec extends FirrtlFlatSpec { val absPath1 = relPath1.addHierarchy("Top", "foo") val absPath2 = relPath2.addHierarchy("Top", "foo") - val renames1 = RenameMap() + val renames1 = MutableRenameMap() renames1.record(dupMod1, absPath1) renames1.record(dupMod2, absPath2) renames1.record(relPath1, absPath1) renames1.record(relPath2, absPath2) - val renames2 = RenameMap() + val renames2 = MutableRenameMap() renames2.record(dupMod1, dedupedMod) renames2.record(dupMod2, dedupedMod) @@ -713,10 +714,10 @@ class RenameMapSpec extends FirrtlFlatSpec { val oldRef = inlineMod.ref("bar") val prefixRef = inlineMod.ref("foo") - val renames1 = RenameMap() + val renames1 = MutableRenameMap() renames1.record(inlineInst, inlineMod) - val renames2 = RenameMap() + val renames2 = MutableRenameMap() renames2.record(oldRef, prefixRef) renames1.andThen(renames2) @@ -728,10 +729,10 @@ class RenameMapSpec extends FirrtlFlatSpec { val oldRef = inlineMod.ref("bar") val prefixRef = inlineMod.ref("foo") - val renames1 = RenameMap() + val renames1 = MutableRenameMap() renames1.record(inlineInst, inlineMod) - val renames2 = RenameMap() + val renames2 = MutableRenameMap() renames2.record(oldRef, prefixRef) inlineRename1.andThen(renames1).andThen(renames2) @@ -756,11 +757,11 @@ class RenameMapSpec extends FirrtlFlatSpec { val bar1 = top.instOf("bar1", "Mod") val bar2 = top.instOf("bar2", "Mod") - val foo1Rename = RenameMap() - val foo2Rename = RenameMap() + val foo1Rename = MutableRenameMap() + val foo2Rename = MutableRenameMap() - val bar1Rename = RenameMap() - val bar2Rename = RenameMap() + val bar1Rename = MutableRenameMap() + val bar2Rename = MutableRenameMap() foo1Rename.record(foo1, foo2) foo2Rename.record(foo2, foo3) @@ -783,7 +784,7 @@ class RenameMapSpec extends FirrtlFlatSpec { val foo = top.instOf("foo", "Mod") val bar = top.instOf("bar", "Mod") - val r = RenameMap() + val r = MutableRenameMap() r.record(foo, bar) r.record(foo, foo) @@ -797,7 +798,7 @@ class RenameMapSpec extends FirrtlFlatSpec { val foo = top.instOf("foo", "Mod") val bar = top.instOf("bar", "Mod") - val r = RenameMap() + val r = MutableRenameMap() r.record(foo, bar) r.record(foo, bar) @@ -812,7 +813,7 @@ class RenameMapSpec extends FirrtlFlatSpec { val Mod = CircuitTarget("Top").module("Mod") val Mod2 = CircuitTarget("Top").module("Mod2") - val r = RenameMap() + val r = MutableRenameMap() r.record(foo, Mod) r.record(Mod, Mod2) @@ -827,7 +828,7 @@ class RenameMapSpec extends FirrtlFlatSpec { val foo = top.instOf("foo", "Mod") val Mod = CircuitTarget("Top").module("Mod") - val r = RenameMap() + val r = MutableRenameMap() r.delete(Mod) r.get(foo) should be(Some(Nil)) @@ -837,7 +838,7 @@ class RenameMapSpec extends FirrtlFlatSpec { // this could happen if the instance name needed to be uniquified to avoid clashes in LowerTypes val top = CircuitTarget("top").module("top") - val r = RenameMap() + val r = MutableRenameMap() val i = top.instOf("i", "child") val i_ = top.instOf("i_", "child") r.record(i, i_) @@ -850,7 +851,7 @@ class RenameMapSpec extends FirrtlFlatSpec { val top = CircuitTarget("top").module("top") val child = CircuitTarget("top").module("child") - val r = RenameMap() + val r = MutableRenameMap() r.record(child.ref("a"), Seq(child.ref("a_0"), child.ref("a_1"))) val i = top.instOf("i", "child") r.get(i.ref("a")) should be(Some(Seq(i.ref("a_0"), i.ref("a_1")))) @@ -861,10 +862,10 @@ class RenameMapSpec extends FirrtlFlatSpec { val top = CircuitTarget("top").module("top") val child = CircuitTarget("top").module("child") - val portRenames = RenameMap() + val portRenames = MutableRenameMap() portRenames.record(child.ref("a"), Seq(child.ref("a_0"), child.ref("a_1"))) - val instanceRenames = RenameMap() + val instanceRenames = MutableRenameMap() val i = top.instOf("i", "child") val i_ = top.instOf("i_", "child") instanceRenames.record(i, i_) diff --git a/src/test/scala/firrtlTests/transforms/ManipulateNamesSpec.scala b/src/test/scala/firrtlTests/transforms/ManipulateNamesSpec.scala index fb516626..00849190 100644 --- a/src/test/scala/firrtlTests/transforms/ManipulateNamesSpec.scala +++ b/src/test/scala/firrtlTests/transforms/ManipulateNamesSpec.scala @@ -12,6 +12,7 @@ import firrtl.transforms.{ ManipulateNamesAllowlistResultAnnotation, ManipulateNamesBlocklistAnnotation } +import firrtl.renamemap.MutableRenameMap import org.scalatest.flatspec.AnyFlatSpec import org.scalatest.matchers.should.Matchers @@ -210,7 +211,7 @@ class ManipulateNamesSpec extends AnyFlatSpec with Matchers { oldTargets = Seq(Seq(`~Foo|Bar`)) ) - val r = RenameMap() + val r = MutableRenameMap() r.delete(`~Foo|prefix_Bar`) a.update(r) should be(empty) @@ -228,7 +229,7 @@ class ManipulateNamesSpec extends AnyFlatSpec with Matchers { oldTargets = Seq(Seq(`~Foo|Bar`), Seq(`~Foo|Baz`)) ) - val r = RenameMap() + val r = MutableRenameMap() r.delete(`~Foo|prefix_Bar`) val ax = a.update(r).collect { |