diff options
| author | Albert Magyar | 2020-07-27 10:14:52 -0700 |
|---|---|---|
| committer | GitHub | 2020-07-27 10:14:52 -0700 |
| commit | 3099fc1721514838f04fbf310c6a14616fc4e99a (patch) | |
| tree | 57e37d731f7f89b3cb0605e3588737644f816c70 /src/test/resources | |
| parent | 3fcfbf363e7e04c759f0523d8c4a43427ccdf4a9 (diff) | |
| parent | 1220a23ac9dfc26dbf5475ef064b644cdd1d7983 (diff) | |
Merge pull request #1528 from freechipsproject/conditionally-scopes
Create new scopes for child statements of Conditionally
Diffstat (limited to 'src/test/resources')
| -rw-r--r-- | src/test/resources/features/ChirrtlMems.fir | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/test/resources/features/ChirrtlMems.fir b/src/test/resources/features/ChirrtlMems.fir index c51e3b78..de5b3cf3 100644 --- a/src/test/resources/features/ChirrtlMems.fir +++ b/src/test/resources/features/ChirrtlMems.fir @@ -14,13 +14,13 @@ circuit ChirrtlMems : raddr <= add(raddr, UInt(1)) infer mport r = ram[raddr], newClock + reg waddr : UInt<4>, clock with : (reset => (reset, UInt(0))) + waddr <= add(waddr, UInt(1)) + when wen : node newerClock = clock - reg waddr : UInt<4>, clock with : (reset => (reset, UInt(0))) - waddr <= add(waddr, UInt(1)) infer mport w = ram[waddr], newerClock w <= waddr - when eq(waddr, UInt(0)) : raddr <= UInt(0) |