Add Support for Parameterized ExtModules and Name Override

Adds support for Integer, Double/Real, and String parameters in external
modules. Also add name field to extmodules so that emitted name can be
different from Firrtl name. This is important because parameterized extmodules
will frequently have differing IO even though they need to be emitted as
instantiating the same Verilog module.

1 files changed, 15 insertions, 0 deletions

diff --git a/src/test/resources/blackboxes/ParameterizedExtModule.v b/src/test/resources/blackboxes/ParameterizedExtModule.v
new file mode 100644
index 00000000..ee6e3ec3
--- /dev/null
+++ b/src/test/resources/blackboxes/ParameterizedExtModule.v
@@ -0,0 +1,15 @@
+
+module ParameterizedExtModule(
+  input [15:0] foo,
+  output [15:0] bar
+);
+  parameter VALUE = 0;
+  parameter STRING = "one";
+  parameter REAL = 1.0;
+  wire [15:0] fizz;
+  wire [15:0] buzz;
+  assign bar = foo + VALUE + fizz + buzz;
+  assign fizz = (STRING == "two")? 2 : (STRING == "one")? 1 : 0;
+  assign buzz = (REAL > 2.5E50)? 2 : (REAL < 0.0)? 1 : 0;
+endmodule
+