From 4b8a0d2af52ceeb3ff5d05082af53bac76744361 Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Thu, 22 Sep 2016 19:10:40 -0700
Subject: Add Support for Parameterized ExtModules and Name Override

Adds support for Integer, Double/Real, and String parameters in external
modules. Also add name field to extmodules so that emitted name can be
different from Firrtl name. This is important because parameterized extmodules
will frequently have differing IO even though they need to be emitted as
instantiating the same Verilog module.
---
 src/test/resources/blackboxes/ParameterizedExtModule.v | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 src/test/resources/blackboxes/ParameterizedExtModule.v

(limited to 'src/test/resources/blackboxes/ParameterizedExtModule.v')

diff --git a/src/test/resources/blackboxes/ParameterizedExtModule.v b/src/test/resources/blackboxes/ParameterizedExtModule.v
new file mode 100644
index 00000000..ee6e3ec3
--- /dev/null
+++ b/src/test/resources/blackboxes/ParameterizedExtModule.v
@@ -0,0 +1,15 @@
+
+module ParameterizedExtModule(
+  input [15:0] foo,
+  output [15:0] bar
+);
+  parameter VALUE = 0;
+  parameter STRING = "one";
+  parameter REAL = 1.0;
+  wire [15:0] fizz;
+  wire [15:0] buzz;
+  assign bar = foo + VALUE + fizz + buzz;
+  assign fizz = (STRING == "two")? 2 : (STRING == "one")? 1 : 0;
+  assign buzz = (REAL > 2.5E50)? 2 : (REAL < 0.0)? 1 : 0;
+endmodule
+
-- 
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