Some ScalaDoc warning fixes

6 files changed, 9 insertions, 9 deletions

diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index 5ef291da..b49af505 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -169,9 +169,9 @@ final case object UnknownForm extends CircuitForm(-1) {
 abstract class Transform extends LazyLogging {
   /** A convenience function useful for debugging and error messages */
   def name: String = this.getClass.getSimpleName
-  /** The [[CircuitForm]] that this transform requires to operate on */
+  /** The [[firrtl.CircuitForm]] that this transform requires to operate on */
   def inputForm: CircuitForm
-  /** The [[CircuitForm]] that this transform outputs */
+  /** The [[firrtl.CircuitForm]] that this transform outputs */
   def outputForm: CircuitForm
   /** Perform the transform, encode renaming with RenameMap, and can
     *   delete annotations
diff --git a/src/main/scala/firrtl/transforms/CheckCombLoops.scala b/src/main/scala/firrtl/transforms/CheckCombLoops.scala
index d2d8b449..d50a027c 100644
--- a/src/main/scala/firrtl/transforms/CheckCombLoops.scala
+++ b/src/main/scala/firrtl/transforms/CheckCombLoops.scala
@@ -35,7 +35,7 @@ object DontCheckCombLoopsAnnotation {
 /** Finds and detects combinational logic loops in a circuit, if any
   * exist. Returns the input circuit with no modifications.
   * 
-  * @throws a CombLoopException if a loop is found
+  * @throws CombLoopException if a loop is found
   * @note Input form: Low FIRRTL
   * @note Output form: Low FIRRTL (identity transform)
   * @note The pass looks for loops through combinational-read memories
diff --git a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
index 48978a7a..24c1c51c 100644
--- a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
+++ b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
@@ -26,7 +26,7 @@ import java.io.{File, FileWriter}
   * eligible for removal. Components marked with a [[DontTouchAnnotation]] will be treated as a
   * circuit sink and thus anything that drives such a marked component will NOT be removed.
   *
-  * This transform preserves deduplication. All instances of a given [[DefModule]] are treated as
+  * This transform preserves deduplication. All instances of a given [[firrtl.ir.DefModule]] are treated as
   * the same individual module. Thus, while certain instances may have dead code due to the
   * circumstances of their instantiation in their parent module, they will still not be removed. To
   * remove such modules, use the [[NoDedupAnnotation]] to prevent deduplication.
diff --git a/src/main/scala/logger/Logger.scala b/src/main/scala/logger/Logger.scala
index 806083d1..4b9038ed 100644
--- a/src/main/scala/logger/Logger.scala
+++ b/src/main/scala/logger/Logger.scala
@@ -319,7 +319,7 @@ object Logger {
 
   /**
     * Adds a list of of className, loglevel tuples to the global (dynamicVar)
-    * See [[testPackageNameMatch]] for a description of how class name matching works
+    * See testPackageNameMatch for a description of how class name matching works
     * @param namesToLevel a list of tuples (class name, log level)
     */
   def setClassLogLevels(namesToLevel: Map[String, LogLevel.Value]): Unit = {
diff --git a/src/main/scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala b/src/main/scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala
index ccd6d9c0..6df6733d 100644
--- a/src/main/scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala
+++ b/src/main/scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala
@@ -12,7 +12,7 @@ import firrtl.Mappers._
 // Scala's mutable collections
 import scala.collection.mutable
 
-/** Ledger tracks [[Circuit]] statistics
+/** Ledger tracks [[firrtl.ir.Circuit]] statistics
   *
   * In this lesson, we want to count the number of muxes in each
   *  module in our design.
@@ -47,7 +47,7 @@ class Ledger {
 
 /** AnalyzeCircuit Transform
   *
-  * Walks [[ir.Circuit]], and records the number of muxes it finds, per module.
+  * Walks [[firrtl.ir.Circuit]], and records the number of muxes it finds, per module.
   *
   * While some compiler frameworks operate on graphs, we represent a Firrtl
   * circuit using a tree representation:
diff --git a/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala b/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala
index 6236703f..87b87004 100644
--- a/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala
+++ b/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala
@@ -14,7 +14,7 @@ import firrtl.Mappers._
 // Scala's mutable collections
 import scala.collection.mutable
 
-/** Ledger tracks [[Circuit]] statistics
+/** Ledger tracks [[firrtl.ir.Circuit]] statistics
   * 
   * In this lesson, we want to calculate the number of muxes, not just in 
   *  a module, but also in any instances it has of other modules, etc.
@@ -63,7 +63,7 @@ class Ledger {
 
 /** AnalyzeCircuit Transform
   *
-  * Walks [[ir.Circuit]], and records the number of muxes and instances it
+  * Walks [[firrtl.ir.Circuit]], and records the number of muxes and instances it
   *  finds, per module.
   *
   * While the Firrtl parser emits a bare form of the IR (located in firrtl.ir._),