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authorChick Markley2017-09-21 11:49:46 -0700
committerGitHub2017-09-21 11:49:46 -0700
commit8dbc6e63b6235af69094eb75050e8a751e22694a (patch)
treeb98acfc637cae6d209b063f408a47f46931f31b3 /src/main
parent893ed22449edf83e6773feff8058d6ceb64ae984 (diff)
Fix problem where wrong verilog file is used. (#661)
When calling verilator in a subdirectory like ./test_run_dir/... verilator will read the verilog file from the current working directory if there is a file there with the right name. This fix specifies the specific path of the verilog file intended.
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/firrtl/util/BackendCompilationUtilities.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/util/BackendCompilationUtilities.scala b/src/main/scala/firrtl/util/BackendCompilationUtilities.scala
index 8f4ab73d..f47ac516 100644
--- a/src/main/scala/firrtl/util/BackendCompilationUtilities.scala
+++ b/src/main/scala/firrtl/util/BackendCompilationUtilities.scala
@@ -102,7 +102,7 @@ trait BackendCompilationUtilities {
val command = Seq(
"verilator",
- "--cc", s"$dutFile.v"
+ "--cc", s"${dir.getAbsolutePath}/$dutFile.v"
) ++
blackBoxVerilogList ++
vSources.flatMap(file => Seq("-v", file.getAbsolutePath)) ++