diff options
| author | Albert Magyar | 2020-05-18 08:25:56 -0700 |
|---|---|---|
| committer | GitHub | 2020-05-18 15:25:56 +0000 |
| commit | 8653734c3eaac2e4a1cc53e545ef11b80b03af4d (patch) | |
| tree | 762c4fd27baaceade78537499cdfc42f5be2fc9b /src/main | |
| parent | 1705980cc447e698ca431c4eca2c91bf73a2aab1 (diff) | |
Canonicalize init of regs with zero as reset in RemoveReset (#1627)
* Fixes #1561
* Add test for zero-reset reg from #1561
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/transforms/RemoveReset.scala | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/transforms/RemoveReset.scala b/src/main/scala/firrtl/transforms/RemoveReset.scala index 530b12d9..2db93626 100644 --- a/src/main/scala/firrtl/transforms/RemoveReset.scala +++ b/src/main/scala/firrtl/transforms/RemoveReset.scala @@ -56,8 +56,9 @@ object RemoveReset extends Transform with DependencyAPIMigration { /* A register is initialized to an invalid expression */ case reg @ DefRegister(_, _, _, _, _, init) if invalids.contains(we(init)) => reg.copy(reset = Utils.zero, init = WRef(reg)) - case reg @ DefRegister(_, rname, _, _, reset, init) - if reset != Utils.zero && reset.tpe != AsyncResetType => + case reg @ DefRegister(_, rname, _, _, Utils.zero, _) => + reg.copy(init = WRef(reg)) // canonicalize + case reg @ DefRegister(_, rname, _, _, reset, init) if reset.tpe != AsyncResetType => // Add register reset to map resets(rname) = Reset(reset, init) reg.copy(reset = Utils.zero, init = WRef(reg)) |