diff options
| author | Schuyler Eldridge | 2018-09-25 12:25:05 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2018-09-26 17:25:24 -0400 |
| commit | 502c8dd35e6f27ed6794dad7ae9bcf4d41cc7474 (patch) | |
| tree | b1000d59ec709a548614a8ebac65ea76d77e603b /src/main | |
| parent | ba12915e9b93685107c503b3f91b96d491c48459 (diff) | |
Enforce port uniqueness in Chirrtl/High Checks
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/passes/CheckChirrtl.scala | 4 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/Checks.scala | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/passes/CheckChirrtl.scala b/src/main/scala/firrtl/passes/CheckChirrtl.scala index 3722fd0d..8f37c8bf 100644 --- a/src/main/scala/firrtl/passes/CheckChirrtl.scala +++ b/src/main/scala/firrtl/passes/CheckChirrtl.scala @@ -31,8 +31,6 @@ object CheckChirrtl extends Pass { class NoTopModuleException(info: Info, name: String) extends PassException( s"$info: A single module must be named $name.") - // TODO FIXME - // - Do we need to check for uniquness on port names? def run (c: Circuit): Circuit = { val errors = new Errors() val moduleNames = (c.modules map (_.name)).toSet @@ -105,6 +103,8 @@ object CheckChirrtl extends Pass { } def checkChirrtlP(mname: String, names: NameSet)(p: Port): Port = { + if (names(p.name)) + errors append new NotUniqueException(NoInfo, mname, p.name) names += p.name (p.tpe map checkChirrtlT(p.info, mname) map checkChirrtlW(p.info, mname)) diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala index 215c5425..4c7458bf 100644 --- a/src/main/scala/firrtl/passes/Checks.scala +++ b/src/main/scala/firrtl/passes/Checks.scala @@ -54,8 +54,6 @@ object CheckHighForm extends Pass { class LsbLargerThanMsbException(info: Info, mname: String, op: String, lsb: Int, msb: Int) extends PassException( s"$info: [module $mname] Primop $op lsb $lsb > $msb.") - // TODO FIXME - // - Do we need to check for uniquness on port names? def run(c: Circuit): Circuit = { val errors = new Errors() val moduleGraph = new ModuleGraph @@ -192,6 +190,8 @@ object CheckHighForm extends Pass { } def checkHighFormP(mname: String, names: NameSet)(p: Port): Port = { + if (names(p.name)) + errors.append(new NotUniqueException(NoInfo, mname, p.name)) names += p.name (p.tpe map checkHighFormT(p.info, mname) map checkHighFormW(p.info, mname)) |