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authorjackkoenig2016-09-23 13:44:57 -0700
committerJack Koenig2016-10-26 15:15:37 -0700
commit4c3b4f4dc10c380a101df75cb561e3f79f1a6abe (patch)
treefeb382146fff5d5496079b6d7c4d3d530bd65cda /src/main
parent4b8a0d2af52ceeb3ff5d05082af53bac76744361 (diff)
Add RawString ExtModule parameter support
While unsafe, this supports Verilog parameter types. Tests now require Verilator 3.884+ to pass.
Diffstat (limited to 'src/main')
-rw-r--r--src/main/antlr4/FIRRTL.g412
-rw-r--r--src/main/scala/firrtl/Emitter.scala1
-rw-r--r--src/main/scala/firrtl/Visitor.scala9
-rw-r--r--src/main/scala/firrtl/ir/IR.scala7
4 files changed, 24 insertions, 5 deletions
diff --git a/src/main/antlr4/FIRRTL.g4 b/src/main/antlr4/FIRRTL.g4
index f4d9d3f8..70716c94 100644
--- a/src/main/antlr4/FIRRTL.g4
+++ b/src/main/antlr4/FIRRTL.g4
@@ -97,6 +97,7 @@ parameter
: 'parameter' id '=' IntLit NEWLINE
| 'parameter' id '=' StringLit NEWLINE
| 'parameter' id '=' DoubleLit NEWLINE
+ | 'parameter' id '=' RawString NEWLINE
;
moduleBlock
@@ -321,7 +322,16 @@ HexDigit
;
StringLit
- : '"' ('\\"'|.)*? '"'
+ : '"' UnquotedString? '"'
+ ;
+
+RawString
+ : '\'' UnquotedString? '\''
+ ;
+
+fragment
+UnquotedString
+ : ('\\"'|~[\r\n])+?
;
FileInfo
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index e3a146e2..5a4420c6 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -89,6 +89,7 @@ class VerilogEmitter extends Emitter {
case StringParam(name, value) =>
val strx = "\"" + VerilogStringLitHandler.escape(value) + "\""
s".${name}($strx)"
+ case RawStringParam(name, value) => s".$name($value)"
}
def emit(x: Any)(implicit w: Writer) { emit(x, 0) }
def emit(x: Any, top: Int)(implicit w: Writer) {
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index 03be0c4e..5e07668a 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -119,10 +119,11 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
private def visitParameter[FirrtlNode](ctx: FIRRTLParser.ParameterContext): Param = {
val name = ctx.id.getText
- (ctx.IntLit, ctx.StringLit, ctx.DoubleLit) match {
- case (int, null, null) => IntParam(name, string2BigInt(int.getText))
- case (null, str, null) => StringParam(name, visitStringLit(str))
- case (null, null, dbl) => DoubleParam(name, dbl.getText.toDouble)
+ (ctx.IntLit, ctx.StringLit, ctx.DoubleLit, ctx.RawString) match {
+ case (int, null, null, null) => IntParam(name, string2BigInt(int.getText))
+ case (null, str, null, null) => StringParam(name, visitStringLit(str))
+ case (null, null, dbl, null) => DoubleParam(name, dbl.getText.toDouble)
+ case (null, null, null, raw) => RawStringParam(name, raw.getText.tail.init) // Remove "\'"s
case _ => throw new Exception(s"Internal error: Visiting impossible parameter ${ctx.getText}")
}
}
diff --git a/src/main/scala/firrtl/ir/IR.scala b/src/main/scala/firrtl/ir/IR.scala
index b9b31427..236a7884 100644
--- a/src/main/scala/firrtl/ir/IR.scala
+++ b/src/main/scala/firrtl/ir/IR.scala
@@ -457,6 +457,13 @@ case class DoubleParam(name: String, value: Double) extends Param {
case class StringParam(name: String, value: StringLit) extends Param {
override def serialize: String = super.serialize + value.serialize
}
+/** Raw String Parameter
+ * Useful for Verilog type parameters
+ * @note Firrtl doesn't guarantee anything about this String being legal in any backend
+ */
+case class RawStringParam(name: String, value: String) extends Param {
+ override def serialize: String = super.serialize + s"'$value'"
+}
/** Base class for modules */
abstract class DefModule extends FirrtlNode with IsDeclaration {