diff options
| author | Schuyler Eldridge | 2020-02-06 10:35:36 -0500 |
|---|---|---|
| committer | GitHub | 2020-02-06 10:35:36 -0500 |
| commit | 39f8563c5e3e737610f46a82f6ceaa52120ef654 (patch) | |
| tree | 8112fc8fe606962ebe55d2f0d4a3bbcf0fd81ecc /src/main | |
| parent | bf0ea92752cfb3db1797b8ffc8ff0c776552b1cf (diff) | |
| parent | 7e3a4240f0ddc24d8effac515b7449df588277da (diff) | |
Merge pull request #1362 from freechipsproject/andr-reduction-base-case
Change zero-width base case for Andr
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/passes/ZeroWidth.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/ZeroWidth.scala b/src/main/scala/firrtl/passes/ZeroWidth.scala index 83fc1b6b..e01cfffc 100644 --- a/src/main/scala/firrtl/passes/ZeroWidth.scala +++ b/src/main/scala/firrtl/passes/ZeroWidth.scala @@ -114,6 +114,7 @@ object ZeroWidth extends Transform { case Seq(x) => x case seq => DoPrim(Cat, seq, consts, tpe) map onExp } + case DoPrim(Andr, Seq(x), _, _) if (bitWidth(x.tpe) == 0) => UIntLiteral(1) // nothing false case other => other.tpe match { case UIntType(IntWidth(ZERO)) => UIntLiteral(ZERO, IntWidth(BigInt(1))) case SIntType(IntWidth(ZERO)) => SIntLiteral(ZERO, IntWidth(BigInt(1))) |