Merge pull request #1362 from freechipsproject/andr-reduction-base-case

Change zero-width base case for Andr

2 files changed, 16 insertions, 0 deletions

diff --git a/src/main/scala/firrtl/passes/ZeroWidth.scala b/src/main/scala/firrtl/passes/ZeroWidth.scala
index 83fc1b6b..e01cfffc 100644
--- a/src/main/scala/firrtl/passes/ZeroWidth.scala
+++ b/src/main/scala/firrtl/passes/ZeroWidth.scala
@@ -114,6 +114,7 @@ object ZeroWidth extends Transform {
         case Seq(x) => x
         case seq => DoPrim(Cat, seq, consts, tpe) map onExp
       }
+    case DoPrim(Andr, Seq(x), _, _) if (bitWidth(x.tpe) == 0) => UIntLiteral(1) // nothing false
     case other => other.tpe match {
       case UIntType(IntWidth(ZERO)) => UIntLiteral(ZERO, IntWidth(BigInt(1)))
       case SIntType(IntWidth(ZERO)) => SIntLiteral(ZERO, IntWidth(BigInt(1)))
diff --git a/src/test/scala/firrtlTests/ZeroWidthTests.scala b/src/test/scala/firrtlTests/ZeroWidthTests.scala
index f1dadcee..96d03d08 100644
--- a/src/test/scala/firrtlTests/ZeroWidthTests.scala
+++ b/src/test/scala/firrtlTests/ZeroWidthTests.scala
@@ -212,6 +212,21 @@ class ZeroWidthTests extends FirrtlFlatSpec {
         |    printf(clk, UInt(1), "%d %d %d\n", x, UInt(0), z)""".stripMargin
       (parse(exec(input)).serialize) should be (parse(check).serialize)
   }
+
+  "Andr of zero-width expression" should "return true" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    input y : UInt<0>
+        |    output x : UInt<1>
+        |    x <= andr(y)""".stripMargin
+    val check =
+      """circuit Top :
+         |  module Top :
+         |    output x : UInt<1>
+         |    x <= UInt<1>(1)""".stripMargin
+      (parse(exec(input))) should be (parse(check))
+  }
 }
 
 class ZeroWidthVerilog extends FirrtlFlatSpec {