diff options
| author | Schuyler Eldridge | 2019-07-24 16:53:43 -0400 |
|---|---|---|
| committer | mergify[bot] | 2019-07-24 20:53:43 +0000 |
| commit | 0512b6c719edca8a19084175e95141ab972aac76 (patch) | |
| tree | 6d2a2c8ec3aa07801ad778968dfe44e4817fdca4 /src/main | |
| parent | 8c6d0f434e8984abe7c5902676933c753fe09e71 (diff) | |
Add ExpandConnects to TopWiringTransform fixup (#1135)
This fixes a bug in the TopWiringTransform when wiring aggregates by
adding ExpandConnects to its list of fixup passes. TopWiringTransform
is MidForm => MidForm, but when wiring aggregates, it will output bulk
connects. This violates the MidForm prerequisite that ExpandConnects
has run. Symptomatically, this will manifest as match errors in
LowerTypes if a user tries to use the TopWiringTransform on
aggregates.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/transforms/TopWiring.scala | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/TopWiring.scala b/src/main/scala/firrtl/transforms/TopWiring.scala index 945deb7e..e884e02b 100644 --- a/src/main/scala/firrtl/transforms/TopWiring.scala +++ b/src/main/scala/firrtl/transforms/TopWiring.scala @@ -7,7 +7,8 @@ import firrtl.ir._ import firrtl.passes.{Pass, InferTypes, ResolveKinds, - ResolveGenders + ResolveGenders, + ExpandConnects } import firrtl.annotations._ import firrtl.Mappers._ @@ -226,6 +227,10 @@ class TopWiringTransform extends Transform { val passes = Seq( InferTypes, ResolveKinds, + ResolveGenders, + ExpandConnects, + InferTypes, + ResolveKinds, ResolveGenders ) passes.foldLeft(circuit) { case (c: Circuit, p: Pass) => p.run(c) } |
