From 0512b6c719edca8a19084175e95141ab972aac76 Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge
Date: Wed, 24 Jul 2019 16:53:43 -0400
Subject: Add ExpandConnects to TopWiringTransform fixup (#1135)

This fixes a bug in the TopWiringTransform when wiring aggregates by
adding ExpandConnects to its list of fixup passes. TopWiringTransform
is MidForm => MidForm, but when wiring aggregates, it will output bulk
connects. This violates the MidForm prerequisite that ExpandConnects
has run. Symptomatically, this will manifest as match errors in
LowerTypes if a user tries to use the TopWiringTransform on
aggregates.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>---
 src/main/scala/firrtl/transforms/TopWiring.scala | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

(limited to 'src/main')

diff --git a/src/main/scala/firrtl/transforms/TopWiring.scala b/src/main/scala/firrtl/transforms/TopWiring.scala
index 945deb7e..e884e02b 100644
--- a/src/main/scala/firrtl/transforms/TopWiring.scala
+++ b/src/main/scala/firrtl/transforms/TopWiring.scala
@@ -7,7 +7,8 @@ import firrtl.ir._
 import firrtl.passes.{Pass,
       InferTypes,
       ResolveKinds,
-      ResolveGenders
+      ResolveGenders,
+      ExpandConnects
       }
 import firrtl.annotations._
 import firrtl.Mappers._
@@ -224,6 +225,10 @@ class TopWiringTransform extends Transform {
   /** Run passes to fix up the circuit of making the new connections  */
   private def fixupCircuit(circuit: Circuit): Circuit = {
     val passes = Seq(
+      InferTypes,
+      ResolveKinds,
+      ResolveGenders,
+      ExpandConnects,
       InferTypes,
       ResolveKinds,
       ResolveGenders
-- 
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