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authorazidar2015-02-13 15:42:47 -0800
committerazidar2015-02-13 15:42:47 -0800
commit4f68f75415eb89427062eb86ff21b0e53bf4cadd (patch)
tree1f6a552e18eed4874a563359e95e5aad87a8ef50 /src/main/stanza/firrtl-ir.stanza
parent4deb61cefa9c0ef7806e3986231865ce59673bc2 (diff)
First commit.
Added stanza as a .zip, changed names from ch to firrtl, and spec.tex is included. need to add installation instructions. TODO's included in README
Diffstat (limited to 'src/main/stanza/firrtl-ir.stanza')
-rw-r--r--src/main/stanza/firrtl-ir.stanza146
1 files changed, 146 insertions, 0 deletions
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
new file mode 100644
index 00000000..1a6df3d5
--- /dev/null
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -0,0 +1,146 @@
+defpackage chipper.ir2 :
+ import core
+ import verse
+
+public definterface Direction
+public val INPUT = new Direction
+public val OUTPUT = new Direction
+public val UNKNOWN-DIR = new Direction
+
+public definterface Width
+public defstruct UnknownWidth <: Width
+public defstruct IntWidth <: Width :
+ width: Int
+
+public defstruct PrimOp
+public val ADD-OP = PrimOp()
+public val ADD-MOD-OP = PrimOp()
+public val SUB-OP = PrimOp()
+public val SUB-MOD-OP = PrimOp()
+public val TIMES-OP = PrimOp()
+public val DIVIDE-OP = PrimOp()
+public val MOD-OP = PrimOp()
+public val SHIFT-LEFT-OP = PrimOp()
+public val SHIFT-RIGHT-OP = PrimOp()
+public val PAD-OP = PrimOp()
+public val BIT-AND-OP = PrimOp()
+public val BIT-OR-OP = PrimOp()
+public val BIT-XOR-OP = PrimOp()
+public val CONCAT-OP = PrimOp()
+public val BIT-SELECT-OP = PrimOp()
+public val BITS-SELECT-OP = PrimOp()
+public val MULTIPLEX-OP = PrimOp()
+public val LESS-OP = PrimOp()
+public val LESS-EQ-OP = PrimOp()
+public val GREATER-OP = PrimOp()
+public val GREATER-EQ-OP = PrimOp()
+public val EQUAL-OP = PrimOp()
+
+public definterface Expression
+public defmulti type (e:Expression) -> Type
+
+public defstruct Ref <: Expression :
+ name: Symbol
+ type: Type [multi => false]
+public defstruct Field <: Expression :
+ exp: Expression
+ name: Symbol
+ type: Type [multi => false]
+public defstruct Index <: Expression :
+ exp: Expression
+ value: Int
+ type: Type [multi => false]
+public defstruct UIntValue <: Expression :
+ value: Int
+ width: Width
+public defstruct SIntValue <: Expression :
+ value: Int
+ width: Width
+public defstruct DoPrim <: Expression :
+ op: PrimOp
+ args: List<Expression>
+ consts: List<Int>
+ type: Type [multi => false]
+public defstruct ReadPort <: Expression :
+ mem: Expression
+ index: Expression
+ type: Type [multi => false]
+
+public definterface Command
+public defstruct LetRec <: Command :
+ entries: List<KeyValue<Symbol, Element>>
+ body: Command
+public defstruct DefWire <: Command :
+ name: Symbol
+ type: Type
+public defstruct DefRegister <: Command :
+ name: Symbol
+ type: Type
+public defstruct DefInstance <: Command :
+ name: Symbol
+ module: Expression
+public defstruct DefMemory <: Command :
+ name: Symbol
+ type: VectorType
+public defstruct DefAccessor <: Command :
+ name: Symbol
+ source: Expression
+ index: Expression
+public defstruct Conditionally <: Command :
+ pred: Expression
+ conseq: Command
+ alt: Command
+public defstruct Begin <: Command :
+ body: List<Command>
+public defstruct Connect <: Command :
+ loc: Expression
+ exp: Expression
+public defstruct EmptyCommand <: Command
+
+public definterface Element
+public defmulti type (e:Element) -> Type
+
+public defstruct Register <: Element :
+ type: Type [multi => false]
+ value: Expression
+ enable: Expression
+public defstruct Memory <: Element :
+ type: Type [multi => false]
+ writers: List<WritePort>
+public defstruct WritePort :
+ index: Expression
+ value: Expression
+ enable: Expression
+public defstruct Node <: Element :
+ type: Type [multi => false]
+ value: Expression
+public defstruct Instance <: Element :
+ type: Type [multi => false]
+ module: Expression
+ ports: List<KeyValue<Symbol,Expression>>
+
+public definterface Type
+public defstruct UIntType <: Type :
+ width: Width
+public defstruct SIntType <: Type :
+ width: Width
+public defstruct BundleType <: Type :
+ ports: List<Port>
+public defstruct VectorType <: Type :
+ type: Type
+ size: Int
+public defstruct UnknownType <: Type
+
+public defstruct Port :
+ name: Symbol
+ direction: Direction
+ type: Type
+
+public defstruct Module :
+ name: Symbol
+ ports: List<Port>
+ body: Command
+
+public defstruct Circuit :
+ modules: List<Module>
+ main: Symbol \ No newline at end of file