diff options
| author | azidar | 2015-06-04 14:56:18 -0700 |
|---|---|---|
| committer | azidar | 2015-06-04 14:56:18 -0700 |
| commit | 06f57fefe8258c7d8149156db7ca01a66f207a5d (patch) | |
| tree | 2598d83574f3675e42e763c18fbb6793b779c8df /src/main/stanza/custom-compiler.stanza | |
| parent | d86272ca9238c12e80e78938bc1dd5a1dc8532da (diff) | |
Fixed fir files so they correctly compile to verilog! Front-end needs to generate as-SInt instead of convert, always. Added fast build to Makefile
Diffstat (limited to 'src/main/stanza/custom-compiler.stanza')
| -rw-r--r-- | src/main/stanza/custom-compiler.stanza | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza index aa21504b..773b63ca 100644 --- a/src/main/stanza/custom-compiler.stanza +++ b/src/main/stanza/custom-compiler.stanza @@ -32,7 +32,7 @@ public defmethod passes (c:InstrumentedVerilog) -> List<Pass> : SplitExp() ToRealIR() SpecialRename(`#,`_) - CheckHighForm(`_) + CheckHighForm(expand-delin) CheckLowForm() Verilog(file(c)) ] |