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authorJim Lawson2017-05-27 20:34:39 -0700
committerJack Koenig2017-05-27 20:34:39 -0700
commit8c9c9e2c341c87607d44026b8fc5457409c707b3 (patch)
tree9fa71fca8dc75524b2565f06c07386894f2583b5 /src/main/scala/tutorial
parent99db604e59e8f052d7628f104eecb2641c6ab9b2 (diff)
Prep for Scala 2.12 (#557)
* Update dependencies and JavaConverters for Scala 2.12 * Bump Scala (and library) version(s). * replace "error" with "Utils.error"; bump Scala version to 2.11.11
Diffstat (limited to 'src/main/scala/tutorial')
-rw-r--r--src/main/scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala4
-rw-r--r--src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/main/scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala b/src/main/scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala
index 3f1dfa46..ccd6d9c0 100644
--- a/src/main/scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala
+++ b/src/main/scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala
@@ -4,7 +4,7 @@ package tutorial
package lesson1
// Compiler Infrastructure
-import firrtl.{Transform, LowForm, CircuitState}
+import firrtl.{Transform, LowForm, CircuitState, Utils}
// Firrtl IR classes
import firrtl.ir.{Circuit, DefModule, Statement, Expression, Mux}
// Map functions
@@ -31,7 +31,7 @@ class Ledger {
case Some(name) => moduleMuxMap(name) = moduleMuxMap.getOrElse(name, 0) + 1
}
def getModuleName: String = moduleName match {
- case None => error("Module name not defined in Ledger!")
+ case None => Utils.error("Module name not defined in Ledger!")
case Some(name) => name
}
def setModuleName(myName: String): Unit = {
diff --git a/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala b/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala
index bdf6f665..6236703f 100644
--- a/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala
+++ b/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala
@@ -4,7 +4,7 @@ package tutorial
package lesson2
// Compiler Infrastructure
-import firrtl.{Transform, LowForm, CircuitState}
+import firrtl.{Transform, LowForm, CircuitState, Utils}
// Firrtl IR classes
import firrtl.ir.{Circuit, DefModule, Statement, DefInstance, Expression, Mux}
// Firrtl compiler's working IR classes (WIR)
@@ -133,7 +133,7 @@ class AnalyzeCircuit extends Transform {
// IR node [[DefInstance]] is previously replaced by WDefInstance, a
// "working" IR node
case DefInstance(info, name, module) =>
- error("All DefInstances should have been replaced by WDefInstances")
+ Utils.error("All DefInstances should have been replaced by WDefInstances")
// Working IR Node [[WDefInstance]] is what the compiler uses
// See src/main/scala/firrtl/WIR.scala for all working IR nodes
case WDefInstance(info, name, module, tpe) =>