All of src/ formatted with scalafmt

1 files changed, 10 insertions, 13 deletions

diff --git a/src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala b/src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala
index 72890c07..1e6d2c72 100644
--- a/src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala
+++ b/src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala
@@ -1,4 +1,3 @@
-
 package firrtl.transforms.formal
 
 import firrtl.ir.{Circuit, EmptyStmt, Statement, Verification}
@@ -6,7 +5,6 @@ import firrtl.{CircuitState, DependencyAPIMigration, MinimumVerilogEmitter, Tran
 import firrtl.options.{Dependency, PreservesAll, StageUtils}
 import firrtl.stage.TransformManager.TransformDependency
 
-
 /**
   * Remove Verification Statements
   *
@@ -14,15 +12,12 @@ import firrtl.stage.TransformManager.TransformDependency
   * This is intended to be required by the Verilog emitter to ensure compatibility
   * with the Verilog 2001 standard.
   */
-class RemoveVerificationStatements extends Transform
-  with DependencyAPIMigration
-  with PreservesAll[Transform] {
+class RemoveVerificationStatements extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
 
-  override def prerequisites: Seq[TransformDependency] = Seq.empty
+  override def prerequisites:         Seq[TransformDependency] = Seq.empty
   override def optionalPrerequisites: Seq[TransformDependency] = Seq(Dependency(ConvertAsserts))
   override def optionalPrerequisiteOf: Seq[TransformDependency] =
-    Seq( Dependency[VerilogEmitter],
-      Dependency[MinimumVerilogEmitter])
+    Seq(Dependency[VerilogEmitter], Dependency[MinimumVerilogEmitter])
 
   private var removedCounter = 0
 
@@ -43,11 +38,13 @@ class RemoveVerificationStatements extends Transform
   def execute(state: CircuitState): CircuitState = {
     val newState = state.copy(circuit = run(state.circuit))
     if (removedCounter > 0) {
-      StageUtils.dramaticWarning(s"$removedCounter verification statements " +
-        "(assert, assume or cover) " +
-        "were removed when compiling to Verilog because the basic Verilog " +
-        "standard does not support them. If this was not intended, compile " +
-        "to System Verilog instead using the `-X sverilog` compiler flag.")
+      StageUtils.dramaticWarning(
+        s"$removedCounter verification statements " +
+          "(assert, assume or cover) " +
+          "were removed when compiling to Verilog because the basic Verilog " +
+          "standard does not support them. If this was not intended, compile " +
+          "to System Verilog instead using the `-X sverilog` compiler flag."
+      )
     }
     newState
   }