All of src/ formatted with scalafmt

3 files changed, 24 insertions, 30 deletions

diff --git a/src/main/scala/firrtl/transforms/formal/AssertSubmoduleAssumptions.scala b/src/main/scala/firrtl/transforms/formal/AssertSubmoduleAssumptions.scala
index 7370fcfb..cdbee495 100644
--- a/src/main/scala/firrtl/transforms/formal/AssertSubmoduleAssumptions.scala
+++ b/src/main/scala/firrtl/transforms/formal/AssertSubmoduleAssumptions.scala
@@ -1,4 +1,3 @@
-
 package firrtl.transforms.formal
 
 import firrtl.ir.{Circuit, Formal, Statement, Verification}
@@ -7,7 +6,6 @@ import firrtl.{CircuitState, DependencyAPIMigration, Transform}
 import firrtl.annotations.NoTargetAnnotation
 import firrtl.options.{PreservesAll, RegisteredTransform, ShellOption}
 
-
 /**
   * Assert Submodule Assumptions
   *
@@ -16,12 +14,13 @@ import firrtl.options.{PreservesAll, RegisteredTransform, ShellOption}
   * overly restrictive assume in a child module can prevent the model checker
   * from searching valid inputs and states in the parent module.
   */
-class AssertSubmoduleAssumptions extends Transform
-  with RegisteredTransform
-  with DependencyAPIMigration
-  with PreservesAll[Transform] {
+class AssertSubmoduleAssumptions
+    extends Transform
+    with RegisteredTransform
+    with DependencyAPIMigration
+    with PreservesAll[Transform] {
 
-  override def prerequisites: Seq[TransformDependency] = Seq.empty
+  override def prerequisites:         Seq[TransformDependency] = Seq.empty
   override def optionalPrerequisites: Seq[TransformDependency] = Seq.empty
   override def optionalPrerequisiteOf: Seq[TransformDependency] =
     firrtl.stage.Forms.MidEmitters
@@ -29,9 +28,10 @@ class AssertSubmoduleAssumptions extends Transform
   val options = Seq(
     new ShellOption[Unit](
       longOption = "no-asa",
-      toAnnotationSeq = (_: Unit) => Seq(
-        DontAssertSubmoduleAssumptionsAnnotation),
-      helpText = "Disable assert submodule assumptions" ) )
+      toAnnotationSeq = (_: Unit) => Seq(DontAssertSubmoduleAssumptionsAnnotation),
+      helpText = "Disable assert submodule assumptions"
+    )
+  )
 
   def assertAssumption(s: Statement): Statement = s match {
     case Verification(Formal.Assume, info, clk, cond, en, msg) =>
@@ -50,8 +50,7 @@ class AssertSubmoduleAssumptions extends Transform
   }
 
   def execute(state: CircuitState): CircuitState = {
-    val noASA = state.annotations.contains(
-      DontAssertSubmoduleAssumptionsAnnotation)
+    val noASA = state.annotations.contains(DontAssertSubmoduleAssumptionsAnnotation)
     if (noASA) {
       logger.info("Skipping assert submodule assumptions")
       state
diff --git a/src/main/scala/firrtl/transforms/formal/ConvertAsserts.scala b/src/main/scala/firrtl/transforms/formal/ConvertAsserts.scala
index ddead331..5928c79c 100644
--- a/src/main/scala/firrtl/transforms/formal/ConvertAsserts.scala
+++ b/src/main/scala/firrtl/transforms/formal/ConvertAsserts.scala
@@ -14,10 +14,8 @@ import firrtl.options.Dependency
 object ConvertAsserts extends Transform with DependencyAPIMigration {
   override def prerequisites = Nil
   override def optionalPrerequisites = Nil
-  override def optionalPrerequisiteOf = Seq(
-    Dependency[VerilogEmitter],
-    Dependency[MinimumVerilogEmitter],
-    Dependency[RemoveVerificationStatements])
+  override def optionalPrerequisiteOf =
+    Seq(Dependency[VerilogEmitter], Dependency[MinimumVerilogEmitter], Dependency[RemoveVerificationStatements])
 
   override def invalidates(a: Transform): Boolean = false
 
@@ -28,7 +26,7 @@ object ConvertAsserts extends Transform with DependencyAPIMigration {
       val stop = Stop(i, 1, clk, gatedNPred)
       msg match {
         case StringLit("") => stop
-        case _ => Block(Print(i, msg, Nil, clk, gatedNPred), stop)
+        case _             => Block(Print(i, msg, Nil, clk, gatedNPred), stop)
       }
     case s => s.mapStmt(convertAsserts)
   }
diff --git a/src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala b/src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala
index 72890c07..1e6d2c72 100644
--- a/src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala
+++ b/src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala
@@ -1,4 +1,3 @@
-
 package firrtl.transforms.formal
 
 import firrtl.ir.{Circuit, EmptyStmt, Statement, Verification}
@@ -6,7 +5,6 @@ import firrtl.{CircuitState, DependencyAPIMigration, MinimumVerilogEmitter, Tran
 import firrtl.options.{Dependency, PreservesAll, StageUtils}
 import firrtl.stage.TransformManager.TransformDependency
 
-
 /**
   * Remove Verification Statements
   *
@@ -14,15 +12,12 @@ import firrtl.stage.TransformManager.TransformDependency
   * This is intended to be required by the Verilog emitter to ensure compatibility
   * with the Verilog 2001 standard.
   */
-class RemoveVerificationStatements extends Transform
-  with DependencyAPIMigration
-  with PreservesAll[Transform] {
+class RemoveVerificationStatements extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
 
-  override def prerequisites: Seq[TransformDependency] = Seq.empty
+  override def prerequisites:         Seq[TransformDependency] = Seq.empty
   override def optionalPrerequisites: Seq[TransformDependency] = Seq(Dependency(ConvertAsserts))
   override def optionalPrerequisiteOf: Seq[TransformDependency] =
-    Seq( Dependency[VerilogEmitter],
-      Dependency[MinimumVerilogEmitter])
+    Seq(Dependency[VerilogEmitter], Dependency[MinimumVerilogEmitter])
 
   private var removedCounter = 0
 
@@ -43,11 +38,13 @@ class RemoveVerificationStatements extends Transform
   def execute(state: CircuitState): CircuitState = {
     val newState = state.copy(circuit = run(state.circuit))
     if (removedCounter > 0) {
-      StageUtils.dramaticWarning(s"$removedCounter verification statements " +
-        "(assert, assume or cover) " +
-        "were removed when compiling to Verilog because the basic Verilog " +
-        "standard does not support them. If this was not intended, compile " +
-        "to System Verilog instead using the `-X sverilog` compiler flag.")
+      StageUtils.dramaticWarning(
+        s"$removedCounter verification statements " +
+          "(assert, assume or cover) " +
+          "were removed when compiling to Verilog because the basic Verilog " +
+          "standard does not support them. If this was not intended, compile " +
+          "to System Verilog instead using the `-X sverilog` compiler flag."
+      )
     }
     newState
   }