diff options
| author | Jack Koenig | 2021-12-21 18:47:18 -0800 |
|---|---|---|
| committer | GitHub | 2021-12-21 18:47:18 -0800 |
| commit | 4f3d1003811aa38d10e32b347c8607414d9be034 (patch) | |
| tree | 07db8aefae4bf9d10dc6ff523fb9c43016dcc05c /src/main/scala/firrtl/passes/VerilogModulusCleanup.scala | |
| parent | 2d197c841c5400c6deaa1592525be6a1d81dc1e2 (diff) | |
Remove some warnings (#2448)
* Fix unreachable code warning by changing match order
Simulation Statements did not previously extend IsDeclaration, but now
they do so their match blocks need to be above IsDeclaration.
* Handle MemoryNoInit case in RtlilEmitter
* Remove use of deprecated logToFile
* Fix uses of LegalizeClocksTransform
Replaced all uses of LegalizeClocksTransform with
LegalizeClocksAndAsyncResetsTransform.
* Remove use of CircuitForm in ZeroWidth
Diffstat (limited to 'src/main/scala/firrtl/passes/VerilogModulusCleanup.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/VerilogModulusCleanup.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala index 03dcf0a3..3ca862b9 100644 --- a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala +++ b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala @@ -33,7 +33,7 @@ object VerilogModulusCleanup extends Pass { Dependency[firrtl.transforms.ReplaceTruncatingArithmetic], Dependency[firrtl.transforms.InlineBitExtractionsTransform], Dependency[firrtl.transforms.InlineAcrossCastsTransform], - Dependency[firrtl.transforms.LegalizeClocksTransform], + Dependency[firrtl.transforms.LegalizeClocksAndAsyncResetsTransform], Dependency[firrtl.transforms.FlattenRegUpdate] ) |