Support Memory Initialization for Simulation and FPGA Flows (#1645)

* Support Memory Initialization for Simulation and FPGA Flows

This adds a minimal annotation that allows users to
influence if memories are randomly initialized,
if all entries are initialized to the same scalar or
if each entry should be initialized to a different value.
We use the init block in order to initialize memories
which is supported by verilator as well as yosys
and has previously been used to randomize the initial
memory contents.

* LowerTypes: error when trying to split up a memory with MemoryInitAnnotation

Currently the MemoryInitAnnotation only works for
ground-type memories.
We catch misuse of this annotation at the point of
the firrtl compiler at which memories on non-ground type
get split up, i.e., the LowerTypes transform.
Chisel should try to prevent annotating non-ground
type memories in the frontend, but it is nice to
have an additional check.

* MemoryInitSpec: test JSON deserialization

* MemoryInitAnnotation: split up into three different annotations instead of exposing MemoryInitValue

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

1 files changed, 35 insertions, 0 deletions

diff --git a/src/main/scala/firrtl/annotations/MemoryInitAnnotation.scala b/src/main/scala/firrtl/annotations/MemoryInitAnnotation.scala
new file mode 100644
index 00000000..44a8e3b5
--- /dev/null
+++ b/src/main/scala/firrtl/annotations/MemoryInitAnnotation.scala
@@ -0,0 +1,35 @@
+// See LICENSE for license details.
+
+package firrtl.annotations
+
+import firrtl.{MemoryArrayInit, MemoryEmissionOption, MemoryInitValue, MemoryRandomInit, MemoryScalarInit}
+
+/**
+ * Represents the initial value of the annotated memory.
+ * While not supported on normal ASIC flows, it can be useful for simulation and FPGA flows.
+ * This annotation is consumed by the verilog emitter.
+ */
+sealed trait MemoryInitAnnotation extends SingleTargetAnnotation[ReferenceTarget] with MemoryEmissionOption {
+  def isRandomInit: Boolean
+}
+
+/** Randomly initialize the `target` memory. This is the same as the default behavior. */
+case class MemoryRandomInitAnnotation(target: ReferenceTarget) extends MemoryInitAnnotation {
+  override def duplicate(n: ReferenceTarget): Annotation = copy(n)
+  override def initValue: MemoryInitValue = MemoryRandomInit
+  override def isRandomInit: Boolean = true
+}
+
+/** Initialize all entries of the `target` memory with the scalar `value`. */
+case class MemoryScalarInitAnnotation(target: ReferenceTarget, value: BigInt) extends MemoryInitAnnotation {
+  override def duplicate(n: ReferenceTarget): Annotation = copy(n)
+  override def initValue: MemoryInitValue = MemoryScalarInit(value)
+  override def isRandomInit: Boolean =  false
+}
+
+/** Initialize the `target` memory with the array of `values` which must be the same size as the memory depth. */
+case class MemoryArrayInitAnnotation(target: ReferenceTarget, values: Seq[BigInt]) extends MemoryInitAnnotation {
+  override def duplicate(n: ReferenceTarget): Annotation = copy(n)
+  override def initValue: MemoryInitValue = MemoryArrayInit(values)
+  override def isRandomInit: Boolean =  false
+}
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