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authorsinofp2022-01-06 04:17:52 +0000
committerGitHub2022-01-06 04:17:52 +0000
commit3e494b5cceda14a73f288a293dd007a82be18bb8 (patch)
treea7a7692b4561509689b8ada5a4a755b1b923ff6a /scripts
parentebad877af9d9fe43a92f64f8b63ca8904834cc4d (diff)
Add FileInfo to asyncResetAlwaysBlocks (#2451)
* Add FileInfo to asyncResetAlwaysBlocks Always blocks need three FileInfo (if, true, false) to show line numbers, but initially, every always blocks only have one FileInfo (false). RemoveReset adds the extra two FileInfo to sync always blocks, so sync always blocks can have line numbers. Async always blocks don't provide their only FileInfo, so there are no line numbers. This commit gives async always block the extra FileInfo to show line numbers for them. This code: ```scala import chisel3._ import chisel3.stage._ import firrtl.CustomDefaultRegisterEmission class Test extends Module with RequireAsyncReset { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val valid = RegInit(false.B) valid := io.in io.out := valid } object Test extends App { new ChiselStage().execute(Array(), Seq( ChiselGeneratorAnnotation(() => new Test()), CustomDefaultRegisterEmission(useInitAsPreset = false, disableRandomization = true) )) } ``` will generate this Verilog: ```verilog module Test( input clock, input reset, input io_in, output io_out ); reg valid; // @[Playground.scala 10:22] assign io_out = valid; // @[Playground.scala 12:10] always @(posedge clock or posedge reset) begin if (reset) begin // @[Playground.scala 10:22] valid <= 1'h0; // @[Playground.scala 10:22] end else begin valid <= io_in; // @[Playground.scala 11:9] end end endmodule ``` they have correct line numbers (10, 10, 11). * Add test for async always block line numbers * Add comment for review
Diffstat (limited to 'scripts')
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