Remove The WriteEmitted Phase (#2390)

1 files changed, 2 insertions, 2 deletions

diff --git a/fuzzer/src/main/scala/firrtl/FirrtlEquivalenceTest.scala b/fuzzer/src/main/scala/firrtl/FirrtlEquivalenceTest.scala
index 23c62758..e48e1297 100644
--- a/fuzzer/src/main/scala/firrtl/FirrtlEquivalenceTest.scala
+++ b/fuzzer/src/main/scala/firrtl/FirrtlEquivalenceTest.scala
@@ -12,9 +12,9 @@ import firrtl._
 import firrtl.annotations.{Annotation, CircuitTarget, ModuleTarget, Target}
 import firrtl.ir.Circuit
 import firrtl.options.Dependency
+import firrtl.options.phases.WriteOutputAnnotations
 import firrtl.stage.{FirrtlCircuitAnnotation, InfoModeAnnotation, OutputFileAnnotation, TransformManager}
 import firrtl.stage.Forms.{VerilogMinimumOptimized, VerilogOptimized}
-import firrtl.stage.phases.WriteEmitted
 import firrtl.transforms.{InlineBooleanExpressions, ManipulateNames}
 import firrtl.util.BackendCompilationUtilities
 
@@ -43,7 +43,7 @@ object FirrtlEquivalenceTestUtils {
   }
 
   private def writeEmitted(state: CircuitState, outputFile: String): Unit = {
-    (new WriteEmitted).transform(state.annotations :+ OutputFileAnnotation(outputFile))
+    (new WriteOutputAnnotations).transform(state.annotations :+ OutputFileAnnotation(outputFile))
   }
 
   def firrtlEquivalenceTestPass(