From 5532d5024f70dc84041560a3e70029deda681e01 Mon Sep 17 00:00:00 2001
From: David Biancolin
Date: Tue, 19 Oct 2021 13:47:35 -0700
Subject: Remove The WriteEmitted Phase (#2390)

---
 fuzzer/src/main/scala/firrtl/FirrtlEquivalenceTest.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'fuzzer')

diff --git a/fuzzer/src/main/scala/firrtl/FirrtlEquivalenceTest.scala b/fuzzer/src/main/scala/firrtl/FirrtlEquivalenceTest.scala
index 23c62758..e48e1297 100644
--- a/fuzzer/src/main/scala/firrtl/FirrtlEquivalenceTest.scala
+++ b/fuzzer/src/main/scala/firrtl/FirrtlEquivalenceTest.scala
@@ -12,9 +12,9 @@ import firrtl._
 import firrtl.annotations.{Annotation, CircuitTarget, ModuleTarget, Target}
 import firrtl.ir.Circuit
 import firrtl.options.Dependency
+import firrtl.options.phases.WriteOutputAnnotations
 import firrtl.stage.{FirrtlCircuitAnnotation, InfoModeAnnotation, OutputFileAnnotation, TransformManager}
 import firrtl.stage.Forms.{VerilogMinimumOptimized, VerilogOptimized}
-import firrtl.stage.phases.WriteEmitted
 import firrtl.transforms.{InlineBooleanExpressions, ManipulateNames}
 import firrtl.util.BackendCompilationUtilities
 
@@ -43,7 +43,7 @@ object FirrtlEquivalenceTestUtils {
   }
 
   private def writeEmitted(state: CircuitState, outputFile: String): Unit = {
-    (new WriteEmitted).transform(state.annotations :+ OutputFileAnnotation(outputFile))
+    (new WriteOutputAnnotations).transform(state.annotations :+ OutputFileAnnotation(outputFile))
   }
 
   def firrtlEquivalenceTestPass(
-- 
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