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| author | azidar | 2015-06-02 15:35:02 -0700 |
|---|---|---|
| committer | azidar | 2015-06-02 15:35:02 -0700 |
| commit | eb5ca3c967c929c8331fd17e04dbd9402e41e986 (patch) | |
| tree | 8bd5b7e62b54376cbc6fc9a8b145a7e345d90b16 /Makefile | |
| parent | 13228ed1bf546ad351ecb82ee094eb71e3fe4749 (diff) | |
Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct low-firrtl syntax. Generates verilog that compiles, but is not correct
Diffstat (limited to 'Makefile')
0 files changed, 0 insertions, 0 deletions