Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct low-firrtl syntax. Generates verilog that compiles, but is not correct

5 files changed, 26 insertions, 24 deletions

diff --git a/TODO b/TODO
index 31319411..0997c219 100644
--- a/TODO
+++ b/TODO
@@ -48,6 +48,7 @@ High-Firrtl
 After adding dynamic assertions, insert bounds check with accessor expansion
 Well-formed low firrtl
    All things only assigned to once
+   Register/ReadPort/WritePort are only in correct spots
 Width inference
    No names
    No Unknowns
@@ -55,6 +56,7 @@ Width inference
    Pad's width is greater than value's width
    pad's width is greater than value's width
    connect can connect from big to small??
+Width pad check?
 
 ======== Other Passes ========
 constant folding (partial eval) pass
diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza
index bb9365ae..22b0c978 100644
--- a/src/main/stanza/flo.stanza
+++ b/src/main/stanza/flo.stanza
@@ -60,11 +60,14 @@ defn pad-widths-e (desired:Int,e:Expression) -> Expression :
          if i > desired : trim(desired, e)
          else : SIntValue(value(e),IntWidth(desired))
       (e:Register) :
-         trim-pad(desired, Register(type(e), pad-widths-e(int-width!(type(e)), value(e)), pad-widths-e(1, enable(e))))
+         val value* = pad-widths-e(desired, value(e))
+         Register(type(value*), value*, pad-widths-e(1, enable(e)))
       (e:ReadPort) :
-         trim-pad(desired, ReadPort(mem(e), self-pad-widths-e(index(e)), type(e), pad-widths-e(1, enable(e))))
+         if int-width!(type(e)) != desired : error("ReadPort has different width than desired")
+         else : ReadPort(mem(e), self-pad-widths-e(index(e)), type(e), pad-widths-e(1, enable(e)))
       (e:WritePort) :
-         trim-pad(desired, WritePort(mem(e), self-pad-widths-e(index(e)), type(e), pad-widths-e(1, enable(e))))
+         if int-width!(type(e)) != desired : error("WritePort has different width than desired")
+         else : WritePort(mem(e), self-pad-widths-e(index(e)), type(e), pad-widths-e(1, enable(e)))
       (e) : error(to-string $ e)
 
 defn pad-widths-s (s:Stmt) -> Stmt :
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 1d209622..8b198c64 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -445,11 +445,12 @@ public defn merge!<?K,?V> (a:HashTable<?K,?V>, b:HashTable<K,V>) :
       a[key(e)] = value(e)
 
 public defn pow (x:Int,y:Int) -> Int :
-   var x* = 1
-   var y* = y
-   while y* != 0 :
-      x* = x* * x
-      y* = y* - 1
-   x*
+   var x* = to-long(1)
+   var y* = to-long(y)
+   while y* != to-long(0) :
+      x* = x* * to-long(x)
+      y* = y* - to-long(1)
+   if x* > to-long(2147483647) : error("Value too big for Int")
+   else : to-int $ to-string(x*)
 
 
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index 50ea1fc1..96778469 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -80,7 +80,8 @@ defn emit (e:Expression) -> String :
             val x = args(e)[0]
             val w = width!(type(x))
             val diff = consts(e)[0] - w
-            ["{{" diff "{" emit(x) "[" w - 1 "]}}, " emit(x) " }"]
+            if w == 0 : [ emit(x) ]
+            else : ["{{" diff "{" emit(x) "[" w - 1 "]}}, " emit(x) " }"]
          AS-UINT-OP : 
             ["$unsigned(" emit(args(e)[0]) ")"]
          AS-SINT-OP : 
@@ -100,7 +101,7 @@ defn emit (e:Expression) -> String :
          BIT-XOR-OP : [emit(args(e)[0]) " ^ " emit(args(e)[1])]
          CONCAT-OP : ["{" emit(args(e)[0]) "," emit(args(e)[1]) "}"]
          BIT-SELECT-OP : [emit(args(e)[0]) "[" consts(e)[0] "]"]
-         BITS-SELECT-OP : [emit(args(e)[0]) "[" consts(e)[1] ":" consts(e)[0] "]"]
+         BITS-SELECT-OP : [emit(args(e)[0]) "[" consts(e)[0] ":" consts(e)[1] "]"]
          BIT-AND-REDUCE-OP : 
             var v = emit(args(e)[0])
             for x in tail(args(e)) do :
@@ -161,14 +162,9 @@ defn emit-module (m:InModule) :
                add(inst-ports[name(s)], ["." name(f) "( " n* " )"])
          (s:DefMemory) :
             val vtype = type(s) as VectorType
-            if seq?(s) :
-               add(regs,["reg  " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"])
-               add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"])
-               add(inits,[name(s) " = {" width!(type(vtype)) "{$random}};"])
-            else :
-               add(regs,["reg  " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"])
-               add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"])
-               add(inits,[name(s) " = {" width!(type(vtype)) "{$random}};"])
+            add(regs,["reg  " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"])
+            add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"])
+            add(inits,["  " name(s) "[initvar] = {" width!(type(vtype)) "{$random}};"])
          (s:DefNode) :
             add(wires,["wire " get-width(type(value(s))) " " name(s) ";"])
             add(assigns,["assign " name(s) " = " emit(value(s)) ";"])
diff --git a/test/riscv-mini/Core.fir b/test/riscv-mini/Core.fir
index 06010573..eaa5697e 100644
--- a/test/riscv-mini/Core.fir
+++ b/test/riscv-mini/Core.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p cwT | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit Core : 
@@ -195,12 +195,12 @@ circuit Core :
     when T_1346 : 
       node T_1347 = eq(addr, UInt<12>(1310))
       when T_1347 : 
-        node T_1348 = dshl(UInt<1>(1), src)
+        node T_1348 = dshl(UInt<1>(1), bits(src,5,0))
         node T_1349 = bit-or(data, T_1348)
         reg_tohost := T_1349
       node T_1350 = eq(addr, UInt<12>(1290))
       when T_1350 : 
-        node T_1351 = dshl(UInt<1>(1), src)
+        node T_1351 = dshl(UInt<1>(1), bits(src,5,0))
         node T_1352 = bit-or(data, T_1351)
         reg_status := T_1352
     node T_1353 = eq(cmd, UInt<2>(3))
@@ -209,12 +209,12 @@ circuit Core :
     when T_1355 : 
       node T_1356 = eq(addr, UInt<12>(1310))
       when T_1356 : 
-        node T_1357 = dshl(UInt<1>(0), src)
+        node T_1357 = dshl(UInt<1>(0), bits(src,5,0))
         node T_1358 = bit-and(data, T_1357)
         reg_tohost := T_1358
       node T_1359 = eq(addr, UInt<12>(1290))
       when T_1359 : 
-        node T_1360 = dshl(UInt<1>(0), src)
+        node T_1360 = dshl(UInt<1>(0), bits(src,5,0))
         node T_1361 = bit-and(data, T_1360)
         reg_status := T_1361
   module Datapath :