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authorazidar2015-04-20 15:21:00 -0700
committerazidar2015-04-20 15:21:00 -0700
commitfe2b96f8bbb5ed8deff6cbc8b377087b53d0c4d2 (patch)
tree21d6472bca4e9281aa5b7e65e66927a98cf2ea4c
parent7617e33993abf9f6be357e0261755a4736c2e085 (diff)
Added more relevant names for split expression
-rw-r--r--TODO6
-rw-r--r--src/main/stanza/passes.stanza19
2 files changed, 15 insertions, 10 deletions
diff --git a/TODO b/TODO
index 1c4f2a17..46ee3536 100644
--- a/TODO
+++ b/TODO
@@ -28,17 +28,15 @@ Well-formed low firrtl
All things only assigned to once
======== Other Passes ========
-Temp Elimination
======== Consultations ========
-Patrick:
- subword accesses (extractor?)
- draft example
Stephen:
width equality
pin stephen on an example
======== Think About ========
+naming for split nodes
+subword accesses
annotation system
zero-width wires
on-reset
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index f05f9482..d8bae00a 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -1730,14 +1730,21 @@ defn split-exp (c:Circuit) :
defn f (s:Stmt) -> False: split-exp-s(s,v)
do(f,s)
(s:Conditionally) : error("Shouldn't be here")
- (s) : add(v,map(split-exp-e{_,v},s))
+ (s:Connect) :
+ match(loc(s)) :
+ (e:WritePort) : add(v,map(split-exp-e{_,v,name(exp(s) as WRef)},s))
+ (e) : add(v,map(split-exp-e{_,v,name(loc(s) as WRef)},s))
+ (s:DefNode) : add(v,map(split-exp-e{_,v,name(s)},s))
+ (s) : add(v,map(split-exp-e{_,v,false},s))
false
- defn split-exp-e (e:Expression,v:Vector<Stmt>) -> Expression :
- match(map(split-exp-e{_,v},e)):
+ defn split-exp-e (e:Expression,v:Vector<Stmt>,n:Symbol|False) -> Expression :
+ match(map(split-exp-e{_,v,n},e)):
(e:Subfield|DoPrim|ReadPort|Register|WritePort) :
- val n = gensym(`T)
- add(v,DefNode(n,e))
- WRef(n,type(e),NodeKind(),UNKNOWN-GENDER)
+ val n* =
+ if n typeof False : gensym(`T)
+ else : to-symbol $ string-join $ [n as Symbol gensym(`#)]
+ add(v,DefNode(n*,e))
+ WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER)
(e) : e
Circuit{_,main(c)} $