More bug fixes

10 files changed, 140 insertions, 106 deletions

diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index d2f9fc0e..2998232f 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -22,7 +22,7 @@ object VerilogCompiler extends Compiler {
   // Copied from Stanza implementation
   val passes = Seq(
     //CheckHighForm,          
-    FromCHIRRTL,
+    //FromCHIRRTL,
     ToWorkingIR,            
     ResolveKinds,
     InferTypes,
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 596c1f93..85a2d759 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -54,8 +54,8 @@ object VerilogEmitter extends Emitter {
    }
    def not_empty (s:ArrayBuffer[_]) : Boolean = if (s.size == 0) false else true
    def rand_string (t:Type) : Seq[Any] = {
-      val wx = ((long_BANG(t) + 31) / 32)
-      Seq("{",wx,"{",ran,"}}")
+      val wx = ((long_BANG(t) + 31) / 32).toInt
+      Seq("{",wx.toString,"{",ran,"}}")
    }
    def emit (x:Any) = emit2(x,0)
    def emit2 (x:Any, top:Int) : Unit = {
@@ -97,12 +97,12 @@ object VerilogEmitter extends Emitter {
             }
          }
          case (s:String) => w.get.write(s)
-         case (i:Int) => w.get.write(i)
-         case (i:Long) => w.get.write(i.toInt)
+         case (i:Int) => w.get.write(i.toString)
+         case (i:Long) => w.get.write(i.toString)
          case (t:VIndent) => w.get.write("   ")
          case (r:VRandom) => w.get.write("$random")
          case (s:Seq[Any]) => {
-            s.foreach((x:Any) => emit2(x.as[Any], top + 1))
+            s.foreach((x:Any) => emit2(x.as[Any].get, top + 1))
             if (top == 0) w.get.write("\n")
          }
       }
@@ -112,14 +112,12 @@ object VerilogEmitter extends Emitter {
    def v_print (e:Expression) = {
       e match {
          case (e:UIntValue) => {
-            val str = e.value.toString
-            val out = str.substring(1,str.length() - 1)
-            w.get.write(long_BANG(tpe(e)).toString + "'" + out)
+            val str = e.value.toString(16)
+            w.get.write(long_BANG(tpe(e)).toString + "'h" + str)
          }
          case (e:SIntValue) => {
-            val str = e.value.toString
-            val out = str.substring(1,str.length() - 1)
-            w.get.write(long_BANG(tpe(e)).toString + "'s" + out)
+            val str = e.value.toString(16)
+            w.get.write(long_BANG(tpe(e)).toString + "'sh" + str)
          }
       }
    }
@@ -153,8 +151,8 @@ object VerilogEmitter extends Emitter {
       doprim.op match {
          case ADD_OP => Seq(cast_if(a0())," + ", cast_if(a1()))
          case ADDW_OP => Seq(cast_if(a0())," + ", cast_if(a1()))
-         case SUB_OP => Seq(cast_if(a0())," _ ", cast_if(a1()))
-         case SUBW_OP => Seq(cast_if(a0())," _ ", cast_if(a1()))
+         case SUB_OP => Seq(cast_if(a0())," - ", cast_if(a1()))
+         case SUBW_OP => Seq(cast_if(a0())," - ", cast_if(a1()))
          case MUL_OP => Seq(cast_if(a0())," * ", cast_if(a1()) )
          case DIV_OP => Seq(cast_if(a0())," / ", cast_if(a1()) )
          case REM_OP => Seq(cast_if(a0())," % ", cast_if(a1()) )
@@ -286,7 +284,7 @@ object VerilogEmitter extends Emitter {
                   at_clock(clk) += Seq(tabs,"end")
                }
                case (e) => {
-                  if (e == r) at_clock(clk) += Seq(tabs,";")
+                  if (weq(e,r)) at_clock(clk) += Seq(tabs,";")
                   else at_clock(clk) += Seq(tabs,r," <= ",e,";")
                }
             }
@@ -296,7 +294,7 @@ object VerilogEmitter extends Emitter {
          add_update(Mux(reset,tv,fv,mux_type_and_widths(tv,fv)),"")
       }
       def update (e:Expression,value:Expression,clk:Expression,en:Expression) = {
-         if (at_clock.contains(clk)) at_clock(clk) = ArrayBuffer[Seq[Any]]()
+         if (!at_clock.contains(clk)) at_clock(clk) = ArrayBuffer[Seq[Any]]()
          if (weq(en,one)) at_clock(clk) += Seq(e," <= ",value,";")
          else {
             at_clock(clk) += Seq("if(",en,") begin")
@@ -321,7 +319,14 @@ object VerilogEmitter extends Emitter {
          for (e <- es) {
             declare("wire",lowered_name(e),tpe(e))
             val ex = WRef(lowered_name(e),tpe(e),kind(e),gender(e))
-            if (gender(e) == FEMALE) assign(ex,netlist(e))
+            if (gender(e) == FEMALE) {
+               if (lowered_name(e) == "interconnect_clk") {
+                  for (x <- netlist) {
+                     print("(" + x._1.e1.serialize() + " -> " + x._2.e1.serialize() + ")")
+                  }
+               }
+               assign(ex,netlist(e))
+            }
          }
       }
       def simulate (clk:Expression,en:Expression,s:Seq[Any]) = {
diff --git a/src/main/scala/firrtl/PrimOps.scala b/src/main/scala/firrtl/PrimOps.scala
index f947be35..c4884ff6 100644
--- a/src/main/scala/firrtl/PrimOps.scala
+++ b/src/main/scala/firrtl/PrimOps.scala
@@ -277,75 +277,70 @@ object PrimOps extends LazyLogging {
          }
          case AND_OP => {
             val t = (t1(),t2()) match {
-               case (t1:UIntType, t2:SIntType) => UIntType(MAX(w1(),w2()))
+               case (_:SIntType|_:UIntType, _:SIntType|_:UIntType) => UIntType(MAX(w1(),w2()))
                case (t1,t2) => UnknownType()
             }
             DoPrim(o,a,c,t)
          }
          case OR_OP => {
             val t = (t1(),t2()) match {
-               case (t1:SIntType, t2:SIntType) => UIntType(MAX(w1(),w2()))
+               case (_:SIntType|_:UIntType, _:SIntType|_:UIntType) => UIntType(MAX(w1(),w2()))
                case (t1,t2) => UnknownType()
             }
             DoPrim(o,a,c,t)
          }
          case XOR_OP => {
             val t = (t1(),t2()) match {
-               case (t1:UIntType, t2:UIntType) => UIntType(MAX(w1(),w2()))
-               case (t1:SIntType, t2:UIntType) => UIntType(MAX(w1(),w2()))
-               case (t1:UIntType, t2:SIntType) => UIntType(MAX(w1(),w2()))
-               case (t1:SIntType, t2:SIntType) => UIntType(MAX(w1(),w2()))
+               case (_:SIntType|_:UIntType, _:SIntType|_:UIntType) => UIntType(MAX(w1(),w2()))
                case (t1,t2) => UnknownType()
             }
             DoPrim(o,a,c,t)
          }
          case AND_REDUCE_OP => {
             val t = (t1()) match {
-               case (t1:UIntType) => BoolType()
-               case (t1:SIntType) => BoolType()
+               case (_:UIntType|_:SIntType) => BoolType()
                case (t1) => UnknownType()
             }
             DoPrim(o,a,c,t)
          }
          case OR_REDUCE_OP => {
             val t = (t1()) match {
-               case (t1:UIntType) => BoolType()
+               case (_:UIntType|_:SIntType) => BoolType()
                case (t1) => UnknownType()
             }
             DoPrim(o,a,c,t)
          }
          case XOR_REDUCE_OP => {
             val t = (t1()) match {
-               case (t1:SIntType) => BoolType()
+               case (_:UIntType|_:SIntType) => BoolType()
                case (t1) => UnknownType()
             }
             DoPrim(o,a,c,t)
          }
          case CONCAT_OP => {
             val t = (t1(),t2()) match {
-               case (t1:SIntType, t2:SIntType) => UIntType(PLUS(w1(),w2()))
+               case (_:UIntType|_:SIntType,_:UIntType|_:SIntType) => UIntType(PLUS(w1(),w2()))
                case (t1, t2) => UnknownType()
             }
             DoPrim(o,a,c,t)
          }
          case BITS_SELECT_OP => {
             val t = (t1()) match {
-               case (t1:UIntType) => UIntType(PLUS(MINUS(c1(),c2()),ONE))
-               case (t1:SIntType) => UIntType(PLUS(MINUS(c1(),c2()),ONE))
+               case (_:UIntType|_:SIntType) => UIntType(PLUS(MINUS(c1(),c2()),ONE))
                case (t1) => UnknownType()
             }
             DoPrim(o,a,c,t)
          }
          case HEAD_OP => {
             val t = (t1()) match {
-               case (t1:UIntType) => UIntType(c1())
+               case (_:UIntType|_:SIntType) => UIntType(c1())
                case (t1) => UnknownType()
             }
             DoPrim(o,a,c,t)
          }
          case TAIL_OP => {
             val t = (t1()) match {
-               case (t1:SIntType) => UIntType(MINUS(w1(),c1()))
+               case (_:UIntType|_:SIntType) => UIntType(MINUS(w1(),c1()))
                case (t1) => UnknownType()
             }
             DoPrim(o,a,c,t)
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index b66b0932..a0170b00 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -450,12 +450,13 @@ object Utils {
         case e:WSubField => e.gender
         case e:WSubIndex => e.gender
         case e:WSubAccess => e.gender
-        case e:PrimOp => MALE
+        case e:DoPrim => MALE
         case e:UIntValue => MALE
         case e:SIntValue => MALE
         case e:Mux => MALE
         case e:ValidIf => MALE
-        case _ => error("Shouldn't be here")
+        case e:WInvalid => MALE
+        case e => println(e); error("Shouldn't be here")
     }}
    def get_gender (s:Stmt) : Gender =
      s match {
@@ -524,6 +525,7 @@ object Utils {
           BundleType(mem_fields)
        }
        case s:DefInstance => UnknownType()
+       case s:WDefInstance => s.tpe
        case _ => UnknownType()
     }}
    def get_name (s:Stmt) : String = {
@@ -560,7 +562,13 @@ object Utils {
    def sMap(f:Stmt => Stmt, stmt: Stmt): Stmt =
       stmt match {
         case w: Conditionally => Conditionally(w.info, w.pred, f(w.conseq), f(w.alt))
-        case b: Begin => Begin(b.stmts.map(f))
+        case b: Begin => {
+           val stmtsx = ArrayBuffer[Stmt]()
+           for (i <- 0 until b.stmts.size) {
+              stmtsx += f(b.stmts(i))
+           }
+           Begin(stmtsx)
+        }
         case s: Stmt => s
       }
    def eMap(f:Expression => Expression, stmt:Stmt) : Stmt =
@@ -648,6 +656,7 @@ object Utils {
          case (c:DefMemory) => DefMemory(c.info,f(c.name), c.data_type, c.depth, c.write_latency, c.read_latency, c.readers, c.writers, c.readwriters)
          case (c:DefNode) => DefNode(c.info,f(c.name),c.value)
          case (c:DefInstance) => DefInstance(c.info,f(c.name), c.module)
+         case (c:WDefInstance) => WDefInstance(c.info,f(c.name), c.module,c.tpe)
          case (c) => c
       }
    }
@@ -758,6 +767,7 @@ object Utils {
          case s: WSubField => s"${s.exp.serialize}.${s.name}"
          case s: WSubIndex => s"${s.exp.serialize}[${s.value}]"
          case s: WSubAccess => s"${s.exp.serialize}[${s.index.serialize}]"
+         case r: WVoid => "VOID"
        } 
        ret + debug(exp)
      }
diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala
index 8ebfa9a6..bbe6a235 100644
--- a/src/main/scala/firrtl/WIR.scala
+++ b/src/main/scala/firrtl/WIR.scala
@@ -3,6 +3,7 @@ package firrtl
 
 import scala.collection.Seq
 import Utils._
+import WrappedExpression._
 
 trait Kind
 case class WireKind() extends Kind
@@ -46,19 +47,19 @@ class WrappedExpression (val e1:Expression) {
                case (e1:SIntValue,e2:SIntValue) => if (e1.value == e2.value) true else false
                   // TODO is this necessary? width(e1) == width(e2) 
                case (e1:WRef,e2:WRef) => e1.name equals e2.name
-               case (e1:WSubField,e2:WSubField) => (e1.name equals e2.name) && (e1.exp == e2.exp)
-               case (e1:WSubIndex,e2:WSubIndex) => (e1.value == e2.value) && (e1.exp == e2.exp)
-               case (e1:WSubAccess,e2:WSubAccess) => (e1.index == e2.index) && (e1.exp == e2.exp)
+               case (e1:WSubField,e2:WSubField) => (e1.name equals e2.name) && weq(e1.exp,e2.exp)
+               case (e1:WSubIndex,e2:WSubIndex) => (e1.value == e2.value) && weq(e1.exp,e2.exp)
+               case (e1:WSubAccess,e2:WSubAccess) => weq(e1.index,e2.index) && weq(e1.exp,e2.exp)
                case (e1:WVoid,e2:WVoid) => true
                case (e1:WInvalid,e2:WInvalid) => true
                case (e1:DoPrim,e2:DoPrim) => {
                   var are_equal = e1.op == e2.op
-                  (e1.args,e2.args).zipped.foreach{ (x,y) => { if (x != y) are_equal = false }}
+                  (e1.args,e2.args).zipped.foreach{ (x,y) => { if (!weq(x,y)) are_equal = false }}
                   (e1.consts,e2.consts).zipped.foreach{ (x,y) => { if (x != y) are_equal = false }}
                   are_equal
                }
-               case (e1:Mux,e2:Mux) => (e1.cond == e2.cond) && (e1.tval == e2.tval) && (e1.fval == e2.fval)
-               case (e1:ValidIf,e2:ValidIf) => (e1.cond == e2.cond) && (e1.value == e2.value)
+               case (e1:Mux,e2:Mux) => weq(e1.cond,e2.cond) && weq(e1.tval,e2.tval) && weq(e1.fval,e2.fval)
+               case (e1:ValidIf,e2:ValidIf) => weq(e1.cond,e2.cond) && weq(e1.value,e2.value)
                case (e1,e2) => false
             }
          }
@@ -119,6 +120,7 @@ class WrappedWidth (val w:Width) {
    def eq (w1:Width,w2:Width) : Boolean = {
       (new WrappedWidth(w1)) == (new WrappedWidth(w2))
    }
+   def ww (w:Width) : WrappedWidth = new WrappedWidth(w)
    override def equals (o:Any) : Boolean = {
       o match {
          case (w2:WrappedWidth) => {
@@ -150,10 +152,10 @@ class WrappedWidth (val w:Width) {
                }
                case (w1:IntWidth,w2:IntWidth) => w1.width == w2.width
                case (w1:PlusWidth,w2:PlusWidth) => 
-                  (w1.arg1 == w2.arg1 && w1.arg2 == w2.arg2) || (w1.arg1 == w2.arg2 && w1.arg2 == w2.arg1)
+                  (ww(w1.arg1) == ww(w2.arg1) && ww(w1.arg2) == ww(w2.arg2)) || (ww(w1.arg1) == ww(w2.arg2) && ww(w1.arg2) == ww(w2.arg1))
                case (w1:MinusWidth,w2:MinusWidth) => 
-                  (w1.arg1 == w2.arg1 && w1.arg2 == w2.arg2) || (w1.arg1 == w2.arg2 && w1.arg2 == w2.arg1)
-               case (w1:ExpWidth,w2:ExpWidth) => w1.arg1 == w2.arg1
+                  (ww(w1.arg1) == ww(w2.arg1) && ww(w1.arg2) == ww(w2.arg2)) || (ww(w1.arg1) == ww(w2.arg2) && ww(w1.arg2) == ww(w2.arg1))
+               case (w1:ExpWidth,w2:ExpWidth) => ww(w1.arg1) == ww(w2.arg1)
                case (w1:UnknownWidth,w2:UnknownWidth) => true
                case (w1,w2) => false
             }
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 89d27733..6c77d35d 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -54,7 +54,7 @@ object PassUtils extends LazyLogging {
        val name = p.name
        logger.debug(s"Starting ${name}")
        val x = p.run(c)
-       logger.debug(x.serialize())
+       //logger.debug(x.serialize())
        logger.debug(s"Finished ${name}")
        executePasses(x, passes.tail)
     }
@@ -122,17 +122,17 @@ object ResolveKinds extends Pass {
          def find (m:Module) = {
             def find_stmt (s:Stmt):Stmt = {
                s match {
-                  case s:DefWire => kinds += (s.name -> WireKind())
-                  case s:DefPoison => kinds += (s.name -> PoisonKind())
-                  case s:DefNode => kinds += (s.name -> NodeKind())
-                  case s:DefRegister => kinds += (s.name -> RegKind())
-                  case s:WDefInstance => kinds += (s.name -> InstanceKind())
-                  case s:DefMemory => kinds += (s.name -> MemKind(s.readers ++ s.writers ++ s.readwriters))
+                  case s:DefWire => kinds(s.name) = WireKind()
+                  case s:DefPoison => kinds(s.name) = PoisonKind()
+                  case s:DefNode => kinds(s.name) = NodeKind()
+                  case s:DefRegister => kinds(s.name) = RegKind()
+                  case s:WDefInstance => kinds(s.name) = InstanceKind()
+                  case s:DefMemory => kinds(s.name) = MemKind(s.readers ++ s.writers ++ s.readwriters)
                   case s => false
                }
                sMap(find_stmt,s)
             }
-            m.ports.foreach { p => kinds += (p.name -> PortKind()) }
+            m.ports.foreach { p => kinds(p.name) = PortKind() }
             m match {
                case m:InModule => find_stmt(m.body)
                case m:ExModule => false
@@ -195,35 +195,35 @@ object InferTypes extends Pass {
             s match {
                case s:DefRegister => {
                   val t = remove_unknowns(get_type(s))
-                  types += (s.name -> t)
+                  types(s.name) = t
                   eMap(infer_types_e _,set_type(s,t))
                }
                case s:DefWire => {
                   val sx = eMap(infer_types_e _,s)
                   val t = remove_unknowns(get_type(sx))
-                  types += (s.name -> t)
+                  types(s.name) = t
                   set_type(sx,t)
                }
                case s:DefPoison => {
                   val sx = eMap(infer_types_e _,s)
                   val t = remove_unknowns(get_type(sx))
-                  types += (s.name -> t)
+                  types(s.name) = t
                   set_type(sx,t)
                }
                case s:DefNode => {
                   val sx = eMap(infer_types_e _,s)
                   val t = remove_unknowns(get_type(sx))
-                  types += (s.name -> t)
+                  types(s.name) = t
                   set_type(sx,t)
                }
                case s:DefMemory => {
                   val t = remove_unknowns(get_type(s))
-                  types += (s.name -> t)
+                  types(s.name) = t
                   val dt = remove_unknowns(s.data_type)
                   set_type(s,dt)
                }
                case s:WDefInstance => {
-                  types += (s.name -> module_types(s.module))
+                  types(s.name) = module_types(s.module)
                   WDefInstance(s.info,s.name,s.module,module_types(s.module))
                }
                case s => eMap(infer_types_e _,sMap(infer_types_s,s))
@@ -231,7 +231,7 @@ object InferTypes extends Pass {
          }
  
          mname = m.name
-         m.ports.foreach(p => types += (p.name -> p.tpe))
+         m.ports.foreach(p => types(p.name) = p.tpe)
          m match {
             case m:InModule => InModule(m.info,m.name,m.ports,infer_types_s(m.body))
             case m:ExModule => m
@@ -248,7 +248,7 @@ object InferTypes extends Pass {
             }
          }
       }
-      modulesx.foreach(m => module_types += (m.name -> module_type(m)))
+      modulesx.foreach(m => module_types(m.name) = module_type(m))
       Circuit(c.info,modulesx.map({m => mname = m.name; infer_types(m)}) , c.main )
    }
 }
@@ -405,8 +405,8 @@ object InferWidths extends Pass {
          val wx = (wMap(remove_cycle(n) _,w)) match {
             case (w:MaxWidth) => MaxWidth(w.args.filter{ w => {
                w match {
-                  case (w:VarWidth) => n equals w.name
-                  case (w) => false
+                  case (w:VarWidth) => !(n equals w.name)
+                  case (w) => true
                }}})
             case (w:MinusWidth) => {
                w.arg1 match {
@@ -433,52 +433,72 @@ object InferWidths extends Pass {
       //;  2) Remove Cycles
       //;  3) Move to solved if not self-recursive
       val u = make_unique(l)
-      //println-debug("======== UNIQUE CONSTRAINTS ========")
-      //for (x <- u) { println-debug(x) }
-      //println-debug("====================================")
+      /*
+      println("======== UNIQUE CONSTRAINTS ========")
+      for (x <- u) { println(x) }
+      println("====================================")
+      */
    
       val f = HashMap[String,Width]()
       val o = ArrayBuffer[String]()
       for (x <- u) {
-         //println-debug("==== SOLUTIONS TABLE ====")
-         //for x in f do : println-debug(x)
-         //println-debug("=========================")
+         /*
+         println("==== SOLUTIONS TABLE ====")
+         for (x <- f) println(x)
+         println("=========================")
+         */
    
          val (n, e) = (x._1, x._2)
-   
          val e_sub = substitute(f)(e)
-         //println-debug(["Solving " n " => " e])
-         //println-debug(["After Substitute: " n " => " e-sub])
-         //println-debug("==== SOLUTIONS TABLE (Post Substitute) ====")
-         //for x in f do : println-debug(x)
-         //println-debug("=========================")
+
+         /*
+         println("Solving " + n + " => " + e)
+         println("After Substitute: " + n + " => " + e_sub)
+         println("==== SOLUTIONS TABLE (Post Substitute) ====")
+         for (x <- f) println(x)
+         println("=========================")
+         */
+
          val ex = remove_cycle(n)(e_sub)
-         //;println-debug(["After Remove Cycle: " n " => " ex])
+
+         /*
+         println("After Remove Cycle: " + n + " => " + ex)
+         */
          if (!self_rec(n,ex)) {
-            //;println-all-debug(["Not rec!: " n " => " ex])
-            //;println-all-debug(["Adding [" n "=>" ex "] to Solutions Table"])
+            /*
+            println("Not rec!: " + n + " => " + ex)
+            println("Adding [" + n + "=>" + ex + "] to Solutions Table")
+            */
             o += n
             f(n) = ex
          }
       }
    
-      //println-debug("Forward Solved Constraints")
-      //for x in f do : println-debug(x)
+      /*
+      println("Forward Solved Constraints")
+      for (x <- f) println(x)
+      */
    
       //; Backwards Solve
       val b = HashMap[String,Width]()
       for (i <- 0 until o.size) {
          val n = o(o.size - 1 - i)
-         //println-all-debug(["SOLVE BACK: [" n " => " f[n] "]"])
-         //println-debug("==== SOLUTIONS TABLE ====")
-         //for x in b do : println-debug(x)
-         //println-debug("=========================")
+         /*
+         println("SOLVE BACK: [" + n + " => " + f(n) + "]")
+         println("==== SOLUTIONS TABLE ====")
+         for (x <- b) println(x)
+         println("=========================")
+         */
          val ex = simplify(b_sub(b)(f(n)))
-         //println-all-debug(["BACK RETURN: [" n " => " ex "]"])
+         /*
+         println("BACK RETURN: [" + n + " => " + ex + "]")
+         */
          b(n) = ex
-         //println-debug("==== SOLUTIONS TABLE (Post backsolve) ====")
-         //for x in b do : println-debug(x)
-         //println-debug("=========================")
+         /*
+         println("==== SOLUTIONS TABLE (Post backsolve) ====")
+         for (x <- b) println(x)
+         println("=========================")
+         */
       }
       b
    }
@@ -687,12 +707,12 @@ object ExpandConnects extends Pass {
                }
             }
             s match {
-               case (s:DefWire) => { genders += (s.name -> BIGENDER); s }
-               case (s:DefRegister) => { genders += (s.name -> BIGENDER); s }
-               case (s:WDefInstance) => { genders += (s.name -> MALE); s }
-               case (s:DefMemory) => { genders += (s.name -> MALE); s }
-               case (s:DefPoison) => { genders += (s.name -> MALE); s }
-               case (s:DefNode) => { genders += (s.name -> MALE); s }
+               case (s:DefWire) => { genders(s.name) = BIGENDER; s }
+               case (s:DefRegister) => { genders(s.name) = BIGENDER; s }
+               case (s:WDefInstance) => { genders(s.name) = MALE; s }
+               case (s:DefMemory) => { genders(s.name) = MALE; s }
+               case (s:DefPoison) => { genders(s.name) = MALE; s }
+               case (s:DefNode) => { genders(s.name) = MALE; s }
                case (s:IsInvalid) => {
                   val n = get_size(tpe(s.exp))
                   val invalids = ArrayBuffer[Stmt]()
@@ -748,7 +768,7 @@ object ExpandConnects extends Pass {
             }
          }
    
-         m.ports.foreach { p => genders += (p.name -> to_gender(p.direction)) }
+         m.ports.foreach { p => genders(p.name) = to_gender(p.direction) }
          InModule(m.info,m.name,m.ports,expand_s(m.body))
       }
    
@@ -965,8 +985,7 @@ object ExpandWhens extends Pass {
             }
          }
          val bodyx = void_all_s(m.body)
-         voids += bodyx
-         InModule(m.info,m.name,m.ports,Begin(voids))
+         InModule(m.info,m.name,m.ports,Begin(Seq(Begin(voids),bodyx)))
       }
       def expand_whens (m:InModule) : Tuple2[HashMap[WrappedExpression,Expression],ArrayBuffer[Stmt]] = {
          val simlist = ArrayBuffer[Stmt]()
@@ -1109,10 +1128,9 @@ object CheckInitialization extends Pass with StanzaPass {
    def run (c:Circuit): Circuit = stanzaPass(c, "check-init")
 }
 
-object ConstProp extends Pass with StanzaPass {
+object ConstProp extends Pass {
    def name = "Constant Propogation"
    var mname = ""
-   def run (c:Circuit): Circuit = stanzaPass(c, "const-prop")
    def const_prop_e (e:Expression) : Expression = {
       eMap(const_prop_e _,e) match {
          case (e:DoPrim) => {
@@ -1141,8 +1159,10 @@ object ConstProp extends Pass with StanzaPass {
                      }
                      case (x) => {
                         if (long_BANG(tpe(e)) == long_BANG(tpe(x))) {
-                           if (tpe(x).typeof[UIntType] != None) x
-                           else DoPrim(AS_UINT_OP,Seq(x),Seq(),tpe(e))
+                           tpe(x) match {
+                              case (t:UIntType) => x
+                              case _ => DoPrim(AS_UINT_OP,Seq(x),Seq(),tpe(e)) 
+                           }
                         }
                         else e
                      }
@@ -1155,7 +1175,7 @@ object ConstProp extends Pass with StanzaPass {
       }
    }
    def const_prop_s (s:Stmt) : Stmt = eMap(const_prop_e _, sMap(const_prop_s _,s))
-   def const_prop (c:Circuit) : Circuit = {
+   def run (c:Circuit): Circuit = {
       val modulesx = c.modules.map{ m => {
          m match {
             case (m:ExModule) => m
diff --git a/src/main/stanza/chirrtl.stanza b/src/main/stanza/chirrtl.stanza
index fc770764..607dbc70 100644
--- a/src/main/stanza/chirrtl.stanza
+++ b/src/main/stanza/chirrtl.stanza
@@ -430,7 +430,7 @@ public defmethod name (b:FromCHIRRTL) -> String : "From CHIRRTL"
 public defmethod short-name (b:FromCHIRRTL) -> String : "from-chirrtl"
 
 defn from-chirrtl (c:Circuit) -> Circuit :
-   val c1 = c-infer-types(c)
+   val c1 = infer-types(c)
    ;println(c1)
    val c2 = infer-mdir(c1)
    ;println(c2)
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 01f6db96..1e7e3066 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -50,9 +50,9 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
       ;RemoveSpecialChars()     
       ;TempElimination()                 ; Needs to check number of uses
       ;===============
-      CInferTypes()
-      CInferMDir()
-      RemoveCHIRRTL()            
+      ;CInferTypes()
+      ;CInferMDir()
+      ;RemoveCHIRRTL()            
       ;===============
       ToWorkingIR()            
       ;===============
diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index 92f1b97e..4cc99049 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -240,7 +240,8 @@ public defn check-high-form (c:Circuit) -> Circuit :
    defn check-high-form-w (w:Width) -> Width :
       match(w) :
          (w:IntWidth) : 
-            if width(w) <= to-long(0) : add(errors,NegWidth())
+            if width(w) <= to-long(0) : 
+               add(errors,NegWidth())
             w
          (w) : w
    defn check-high-form-t (t:Type) -> Type :
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index 139216c3..c0e52e45 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -328,6 +328,7 @@ defsyntax firrtl :
                   (w:IntWidth) :
                      if to-long(req-num-bits(b)) > width(w) :
                         FPE(form, "Width too small for UIntValue.")
+                     if width(w) == to-long(0) : println("is zero at")
                      UIntValue(b, w)
                   (w) :
                      ;UIntValue(b, w)